binutils archive
subject index for November, 2015

This is the mail archive of the binutils@sourceware.org mailing list for the binutils project.

Indexes: [Date Index] [Subject Index] [Author Index] [Thread Index]
Site Nav: [Browse other archives for this mailing list]
[Browse other mailing lists at this site]
Search: Limit to:

Re: [16/16][binutils][AARCH64]Add relocation support for large memory model. [LD]Add TLSIE relaxation support.

[AArch64] Add ARMv8.2 command line option and feature flag.

[AArch64] Add feature flags and command line for ARMv8.2 FP16 support.

[AArch64] Let aliased instructions be their preferred form.

[AArch64] Reject invalid immediate operands to MSR PAN

[Aarch64] Support an ARMv8.2 system register.

[AArch64][binutils] Add support for ARMv8.1 Virtulization Host Extensions

[AArch64][PATCH 1/2] Add ARMv8.2 instructions BFC and REV64.

[AArch64][PATCH 1/3] Support ARMv8.2 FP16 floating point instructions.

[AArch64][PATCH 2/2] Add ARMv8.2 instruction alias REV64.

[AArch64][PATCH 2/3] Adjust a utility function for floating point values.

[AArch64][PATCH 3/3] Add floating-point FP16 instructions

[ARM] Add ARMv8.2 architecture feature and command line option.

[ARM] testsuite remaining errors

[ARM][GAS] Fix invalid arm-wince-pe tests.

[ARM][PR gas/19217] Fix wrong use of MOVT to replace LDR

[binutils][2.25][objdump][ARM][PATCH 0/2] Backport fixes for unpredictable nops and 26-bit versions of teq,tst,cmn,cmp

[binutils][2.25][objdump][ARM][PATCH 1/2] Backport fixes for unpredictable nops and 26-bit versions of teq, tst, cmn, cmp

[binutils][2.25][objdump][ARM][PATCH 2/2] Backport Tests for 26-bit versions of teq, tst, cmn, cmp

[Committed] S/390: Fix PR19263

[gold commit] PR 19244: Fix problem where symbols for copy relocations are marked local

[gold commit] PR gold/19291: Adjust local symbol value in relocatable link to be relative to section

[GOLD] Add more params to relocate() and relocate_section()

[GOLD] Align PowerPC64 GOT

[GOLD] Edit PowerPC64 ELFv2 function entry code

[GOLD] PowerPC TOC16 and GOT16 relocs are relative

[GOLD] R_PPC64_ENTRY support

[GOLD] Regenerate POTFILES.in to add s390.cc

Re: [gold][aarch64] PR gold/19163: zero-out ABS64/32/16/ in .rela.dyn.

[LD, ARM] Fix in STM32L4XX patch

[LD][AARCH64]Create test cases for big-endian

[Mach-O, committed]: cleanup and support new load commands

[Mach-O, committed]: Dump compact unwind entries for arm64

[Mach-O, committed]: support recent versions of Mach-O

[Mach-O, committed]: Use a per-target reloc canonicalise function.

[Mach-O] Fix previous patch

[Mach-O]: Add support for arm and aarch64 for darwin

Re: [PATCH 0/7] Fix invalid left shift of negative value.

[PATCH 1/6] gold: Add 2 overloaded functions to copy_reloc.

[PATCH 2/6] gold: Recognize .pdr debug sections.

[PATCH 3/6] gold: Take addend into account for calculating value of the local symbol for GOT.

[PATCH 4/6] gold: Correctly get and put r_info for Mips64el.

Re: [PATCH 4/7] Fix invalid left shift of negative value.

[PATCH 5/6] gold: Add Mips64 support.

Re: [PATCH 5/7] Fix invalid left shift of negative value.

[PATCH 6/6] gold: Fix non-deterministic behaviour of Mips gold.

Re: [PATCH 6/7] Fix invalid left shift of negative value.

Re: [PATCH 7/7] Fix invalid left shift of negative value.

[Patch Gas AArch64] Add support for Cortex-A35

[Patch Gas ARM] Add support for Cortex-A35

[PATCH v2 1/4] gold: Take addend into account for calculating value of the local symbol for GOT.

[PATCH v2 2/4] gold: Correctly get and put r_info for Mips64el.

[PATCH v2 3/4] gold: Add Mips64 support.

[PATCH v2 4/4] gold: Fix non-deterministic behaviour of Mips gold.

[PATCH, COMMITTED] Add full Power ISA 3.0 / POWER9 binutils support

Re: [PATCH] 'add symbol' feature in objcopy

[PATCH] [ARM/AARCH64] add initial Qualcomm processor support

[PATCH] [GAS, ARM] Invalid LDR immediate transformation

Re: [PATCH] [GAS, ARM] Invalid LDR immediate transformation

[PATCH] [GAS] sparc: support %dN and %qN syntax for FP registers.

[PATCH] [RFC] nios2: Fix initial PLT entry population

Re: [PATCH] add a configure option for using RELRO by default

[PATCH] ARM: Add support for thumb1 PCROP relocations.

[PATCH] gas: microblaze: fix shift overflow

[PATCH] gold: Implement --long-plt flag.

Re: [PATCH] MIPS support for --hash-style=gnu

[PATCH] MIPS/GAS/testsuite: Tighten negative-match NaN tests

[PATCH] MIPS/LD: Fix little-endian `mti' and `img' ELF emulations

Re: [PATCH] MIPS: Enable tlbinv and tlbinvf instructions for microMIPS; and mips32r3 and above

[PATCH] objdump: Handle 32-bit base address in debug_ranges / debug_loc.

[Patch]: arm disassembler: handle arm vs thumb for Mach-O

[PATCH][Binutils][ARM] ldah being disassembled as ldaexh

RE: [PATCH][MIPS] Move copy_u.w to MSA64 ASE, remove copy_u.d

[Proposed patch] Huge performance regression in ld -r since binutils >= 2.21

[RFC PATCH 00/11] binutils: MIPS IEEE Std 754 NaN interlinking support

[RFC PATCH 01/11] MIPS/BFD: Correct an FP ABI warning

[RFC PATCH 02/11] MIPS/BFD: Use local pointers to target data in private data merge

[RFC PATCH 03/11] MIPS/BFD: Suppress attribute checks for null input

[RFC PATCH 04/11] MIPS/BFD: Fold the handling of input MIPS ABI flags together

[RFC PATCH 05/11] MIPS/BFD: Factor out ELF file header flag checks

[RFC PATCH 06/11] MIPS/BFD: Propagate the return status in attribute merging

[RFC PATCH 07/11] MIPS/BFD: Move attribute check after ELF file header flag check

[RFC PATCH 08/11] MIPS/BFD: Factor out ABI flag merging

[RFC PATCH 09/11] MIPS/LD: Convert ELF linker emulation option macros to an enum

[RFC PATCH 10/11] BFD: Pass link information to `bfd_merge_private_bfd_data'

[RFC PATCH 11/11] MIPS: IEEE Std 754 NaN interlinking support

Re: [RFC] Add IFUNC support for MIPS (v3)

[RFC] MIPS ABI Extension for IEEE Std 754 Non-Compliant Interlinking

Account for .tbss alignment when adjusting start of relro

Add link library at runtime?

ARC port broken reloc processing

Commit: RX: Disassemble NOP instructions

Commit: RX: Fix assembler's handling of section alignment parameter

Commit: RX: Fix disassembly of erroneous conditionals

Commit: RX: Fix disassembly of zero-offset register indirect instructions

DATA_SEGMENT_ALIGN documentation is not consistent with behaviour

Dwp tool heap usage, reducing the memory foot-print.

FYI, merged libiberty/, config/ and include/ from GCC

Import Microblaze fix into 2.26 branch

Linking problems on CentOS 4.9

Re: Make only binaries/libs or disable-doc

Re: MinGW ld from msys2 crashes on Wine when linking MinGW xz, valgrind reports "Invalid read of size 4"

MSP430: Fix problem initialising .upper.bss section

New Catalan PO file for 'binutils' (version 2.24.90)

Re: New Chinese (simplified) PO file for 'opcodes' (version 2.24.90)

New French PO file for 'gas' (version 2.26.51)

New template for 'gas' made available

New Ukrainian PO file for 'gas' (version 2.26.51)

output_big_leb128 comment

PATCH: fix sleb128 for 64 vs 32 host

Patch: Support toc relative access to dynamic symbols from static code.

Prevent looping in archives

R_PPC64_ENTRY

readelf verdef and verneed

Recent powerpc testcase fails

Release 0.26: branch created.

Release 0.26: branching

SPARC: nested static initialization

Unable to clone git repo thought https

update zlib to 1.2.8

Use default sub-segment align for non-ELF powerpc

VMA format in linker map file on 64-bit host for 32-bit target.

Indexes: [Date Index] [Subject Index] [Author Index] [Thread Index]
Site Nav: [Browse other archives for this mailing list]
[Browse other mailing lists at this site]
Search: Limit to:
Mail converted by MHonArc