[PATCH 2/2][Aarch64][gas] Add support for ARMv8.1a Adv.SIMD instructions.

[Matthew Wahab <matthew dot wahab at arm dot com>]

ARMv8.1a adds two instructions, SQRDMLAH and SQRDMLSH, to the Aarch64 SIMD
instruction set. This patch adds support to gas for these instructions
under the new architecture extension "rdma".

Tested aarch64-none-linux-gnu with check-gas and check-binutils.

Ok for trunk?
Matthew

gas/
2015-05-20  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (aarch64_features): Add "rdma".
	* doc/c-aarch64.texi (AArch64 Extensions): Add "rdma".

gas/testsuite/
2015-05-20  Matthew Wahab  <matthew.wahab@arm.com>

	* rdma-directive.d: New.
	* rdma.d: New.
	* rdma.s: New.


diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index ae0e2d6..780d1ef 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -7366,6 +7366,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"fp",		AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
   {"lse",		AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0)},
   {"simd",		AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
+  {"rdma",		AARCH64_FEATURE (AARCH64_FEATURE_SIMD
+					 | AARCH64_FEATURE_RDMA, 0)},
   {NULL,		AARCH64_ARCH_NONE}
 };
 
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 79fe168..f7fdb52 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -133,6 +133,8 @@ automatically cause those extensions to be disabled.
  @tab Enable floating-point extensions.
 @item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
+@item @code{rdma} @tab ARMv8-A @tab ARMv8-A or later
+ @tab Enable ARMv8.1 Advanced SIMD extensions.  This implies @code{simd}.
 @end multitable
 
 @node AArch64 Syntax
diff --git a/gas/testsuite/gas/aarch64/rdma-directive.d b/gas/testsuite/gas/aarch64/rdma-directive.d
new file mode 100644
index 0000000..bd2e818
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/rdma-directive.d
@@ -0,0 +1,70 @@
+#objdump: -dr
+#as: --defsym DIRECTIVE=1
+#source: rdma.s
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+   0:	2e428420 	sqrdmlah	v0\.4h, v1\.4h, v2\.4h
+   4:	6e428420 	sqrdmlah	v0\.8h, v1\.8h, v2\.8h
+   8:	2e828420 	sqrdmlah	v0\.2s, v1\.2s, v2\.2s
+   c:	6e828420 	sqrdmlah	v0\.4s, v1\.4s, v2\.4s
+  10:	2e428c20 	sqrdmlsh	v0\.4h, v1\.4h, v2\.4h
+  14:	6e428c20 	sqrdmlsh	v0\.8h, v1\.8h, v2\.8h
+  18:	2e828c20 	sqrdmlsh	v0\.2s, v1\.2s, v2\.2s
+  1c:	6e828c20 	sqrdmlsh	v0\.4s, v1\.4s, v2\.4s
+  20:	7e828420 	sqrdmlah	s0, s1, s2
+  24:	7e428420 	sqrdmlah	h0, h1, h2
+  28:	7e828c20 	sqrdmlsh	s0, s1, s2
+  2c:	7e428c20 	sqrdmlsh	h0, h1, h2
+  30:	2f42d020 	sqrdmlah	v0\.4h, v1\.4h, v2\.h\[0\]
+  34:	2f52d020 	sqrdmlah	v0\.4h, v1\.4h, v2\.h\[1\]
+  38:	2f62d020 	sqrdmlah	v0\.4h, v1\.4h, v2\.h\[2\]
+  3c:	2f72d020 	sqrdmlah	v0\.4h, v1\.4h, v2\.h\[3\]
+  40:	6f42d020 	sqrdmlah	v0\.8h, v1\.8h, v2\.h\[0\]
+  44:	6f52d020 	sqrdmlah	v0\.8h, v1\.8h, v2\.h\[1\]
+  48:	6f62d020 	sqrdmlah	v0\.8h, v1\.8h, v2\.h\[2\]
+  4c:	6f72d020 	sqrdmlah	v0\.8h, v1\.8h, v2\.h\[3\]
+  50:	2f82d020 	sqrdmlah	v0\.2s, v1\.2s, v2\.s\[0\]
+  54:	2fa2d020 	sqrdmlah	v0\.2s, v1\.2s, v2\.s\[1\]
+  58:	2f82d820 	sqrdmlah	v0\.2s, v1\.2s, v2\.s\[2\]
+  5c:	2fa2d820 	sqrdmlah	v0\.2s, v1\.2s, v2\.s\[3\]
+  60:	6f82d020 	sqrdmlah	v0\.4s, v1\.4s, v2\.s\[0\]
+  64:	6fa2d020 	sqrdmlah	v0\.4s, v1\.4s, v2\.s\[1\]
+  68:	6f82d820 	sqrdmlah	v0\.4s, v1\.4s, v2\.s\[2\]
+  6c:	6fa2d820 	sqrdmlah	v0\.4s, v1\.4s, v2\.s\[3\]
+  70:	2f42f020 	sqrdmlsh	v0\.4h, v1\.4h, v2\.h\[0\]
+  74:	2f52f020 	sqrdmlsh	v0\.4h, v1\.4h, v2\.h\[1\]
+  78:	2f62f020 	sqrdmlsh	v0\.4h, v1\.4h, v2\.h\[2\]
+  7c:	2f72f020 	sqrdmlsh	v0\.4h, v1\.4h, v2\.h\[3\]
+  80:	6f42f020 	sqrdmlsh	v0\.8h, v1\.8h, v2\.h\[0\]
+  84:	6f52f020 	sqrdmlsh	v0\.8h, v1\.8h, v2\.h\[1\]
+  88:	6f62f020 	sqrdmlsh	v0\.8h, v1\.8h, v2\.h\[2\]
+  8c:	6f72f020 	sqrdmlsh	v0\.8h, v1\.8h, v2\.h\[3\]
+  90:	2f82f020 	sqrdmlsh	v0\.2s, v1\.2s, v2\.s\[0\]
+  94:	2fa2f020 	sqrdmlsh	v0\.2s, v1\.2s, v2\.s\[1\]
+  98:	2f82f820 	sqrdmlsh	v0\.2s, v1\.2s, v2\.s\[2\]
+  9c:	2fa2f820 	sqrdmlsh	v0\.2s, v1\.2s, v2\.s\[3\]
+  a0:	6f82f020 	sqrdmlsh	v0\.4s, v1\.4s, v2\.s\[0\]
+  a4:	6fa2f020 	sqrdmlsh	v0\.4s, v1\.4s, v2\.s\[1\]
+  a8:	6f82f820 	sqrdmlsh	v0\.4s, v1\.4s, v2\.s\[2\]
+  ac:	6fa2f820 	sqrdmlsh	v0\.4s, v1\.4s, v2\.s\[3\]
+  b0:	7f42d020 	sqrdmlah	h0, h1, v2\.h\[0\]
+  b4:	7f52d020 	sqrdmlah	h0, h1, v2\.h\[1\]
+  b8:	7f62d020 	sqrdmlah	h0, h1, v2\.h\[2\]
+  bc:	7f72d020 	sqrdmlah	h0, h1, v2\.h\[3\]
+  c0:	7f82d020 	sqrdmlah	s0, s1, v2\.s\[0\]
+  c4:	7fa2d020 	sqrdmlah	s0, s1, v2\.s\[1\]
+  c8:	7f82d820 	sqrdmlah	s0, s1, v2\.s\[2\]
+  cc:	7fa2d820 	sqrdmlah	s0, s1, v2\.s\[3\]
+  d0:	7f42f020 	sqrdmlsh	h0, h1, v2\.h\[0\]
+  d4:	7f52f020 	sqrdmlsh	h0, h1, v2\.h\[1\]
+  d8:	7f62f020 	sqrdmlsh	h0, h1, v2\.h\[2\]
+  dc:	7f72f020 	sqrdmlsh	h0, h1, v2\.h\[3\]
+  e0:	7f82f020 	sqrdmlsh	s0, s1, v2\.s\[0\]
+  e4:	7fa2f020 	sqrdmlsh	s0, s1, v2\.s\[1\]
+  e8:	7f82f820 	sqrdmlsh	s0, s1, v2\.s\[2\]
+  ec:	7fa2f820 	sqrdmlsh	s0, s1, v2\.s\[3\]
diff --git a/gas/testsuite/gas/aarch64/rdma.d b/gas/testsuite/gas/aarch64/rdma.d
new file mode 100644
index 0000000..2ffde68
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/rdma.d
@@ -0,0 +1,69 @@
+#objdump: -dr
+#as: -march=armv8-a+rdma
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+   0:	2e428420 	sqrdmlah	v0\.4h, v1\.4h, v2\.4h
+   4:	6e428420 	sqrdmlah	v0\.8h, v1\.8h, v2\.8h
+   8:	2e828420 	sqrdmlah	v0\.2s, v1\.2s, v2\.2s
+   c:	6e828420 	sqrdmlah	v0\.4s, v1\.4s, v2\.4s
+  10:	2e428c20 	sqrdmlsh	v0\.4h, v1\.4h, v2\.4h
+  14:	6e428c20 	sqrdmlsh	v0\.8h, v1\.8h, v2\.8h
+  18:	2e828c20 	sqrdmlsh	v0\.2s, v1\.2s, v2\.2s
+  1c:	6e828c20 	sqrdmlsh	v0\.4s, v1\.4s, v2\.4s
+  20:	7e828420 	sqrdmlah	s0, s1, s2
+  24:	7e428420 	sqrdmlah	h0, h1, h2
+  28:	7e828c20 	sqrdmlsh	s0, s1, s2
+  2c:	7e428c20 	sqrdmlsh	h0, h1, h2
+  30:	2f42d020 	sqrdmlah	v0\.4h, v1\.4h, v2\.h\[0\]
+  34:	2f52d020 	sqrdmlah	v0\.4h, v1\.4h, v2\.h\[1\]
+  38:	2f62d020 	sqrdmlah	v0\.4h, v1\.4h, v2\.h\[2\]
+  3c:	2f72d020 	sqrdmlah	v0\.4h, v1\.4h, v2\.h\[3\]
+  40:	6f42d020 	sqrdmlah	v0\.8h, v1\.8h, v2\.h\[0\]
+  44:	6f52d020 	sqrdmlah	v0\.8h, v1\.8h, v2\.h\[1\]
+  48:	6f62d020 	sqrdmlah	v0\.8h, v1\.8h, v2\.h\[2\]
+  4c:	6f72d020 	sqrdmlah	v0\.8h, v1\.8h, v2\.h\[3\]
+  50:	2f82d020 	sqrdmlah	v0\.2s, v1\.2s, v2\.s\[0\]
+  54:	2fa2d020 	sqrdmlah	v0\.2s, v1\.2s, v2\.s\[1\]
+  58:	2f82d820 	sqrdmlah	v0\.2s, v1\.2s, v2\.s\[2\]
+  5c:	2fa2d820 	sqrdmlah	v0\.2s, v1\.2s, v2\.s\[3\]
+  60:	6f82d020 	sqrdmlah	v0\.4s, v1\.4s, v2\.s\[0\]
+  64:	6fa2d020 	sqrdmlah	v0\.4s, v1\.4s, v2\.s\[1\]
+  68:	6f82d820 	sqrdmlah	v0\.4s, v1\.4s, v2\.s\[2\]
+  6c:	6fa2d820 	sqrdmlah	v0\.4s, v1\.4s, v2\.s\[3\]
+  70:	2f42f020 	sqrdmlsh	v0\.4h, v1\.4h, v2\.h\[0\]
+  74:	2f52f020 	sqrdmlsh	v0\.4h, v1\.4h, v2\.h\[1\]
+  78:	2f62f020 	sqrdmlsh	v0\.4h, v1\.4h, v2\.h\[2\]
+  7c:	2f72f020 	sqrdmlsh	v0\.4h, v1\.4h, v2\.h\[3\]
+  80:	6f42f020 	sqrdmlsh	v0\.8h, v1\.8h, v2\.h\[0\]
+  84:	6f52f020 	sqrdmlsh	v0\.8h, v1\.8h, v2\.h\[1\]
+  88:	6f62f020 	sqrdmlsh	v0\.8h, v1\.8h, v2\.h\[2\]
+  8c:	6f72f020 	sqrdmlsh	v0\.8h, v1\.8h, v2\.h\[3\]
+  90:	2f82f020 	sqrdmlsh	v0\.2s, v1\.2s, v2\.s\[0\]
+  94:	2fa2f020 	sqrdmlsh	v0\.2s, v1\.2s, v2\.s\[1\]
+  98:	2f82f820 	sqrdmlsh	v0\.2s, v1\.2s, v2\.s\[2\]
+  9c:	2fa2f820 	sqrdmlsh	v0\.2s, v1\.2s, v2\.s\[3\]
+  a0:	6f82f020 	sqrdmlsh	v0\.4s, v1\.4s, v2\.s\[0\]
+  a4:	6fa2f020 	sqrdmlsh	v0\.4s, v1\.4s, v2\.s\[1\]
+  a8:	6f82f820 	sqrdmlsh	v0\.4s, v1\.4s, v2\.s\[2\]
+  ac:	6fa2f820 	sqrdmlsh	v0\.4s, v1\.4s, v2\.s\[3\]
+  b0:	7f42d020 	sqrdmlah	h0, h1, v2\.h\[0\]
+  b4:	7f52d020 	sqrdmlah	h0, h1, v2\.h\[1\]
+  b8:	7f62d020 	sqrdmlah	h0, h1, v2\.h\[2\]
+  bc:	7f72d020 	sqrdmlah	h0, h1, v2\.h\[3\]
+  c0:	7f82d020 	sqrdmlah	s0, s1, v2\.s\[0\]
+  c4:	7fa2d020 	sqrdmlah	s0, s1, v2\.s\[1\]
+  c8:	7f82d820 	sqrdmlah	s0, s1, v2\.s\[2\]
+  cc:	7fa2d820 	sqrdmlah	s0, s1, v2\.s\[3\]
+  d0:	7f42f020 	sqrdmlsh	h0, h1, v2\.h\[0\]
+  d4:	7f52f020 	sqrdmlsh	h0, h1, v2\.h\[1\]
+  d8:	7f62f020 	sqrdmlsh	h0, h1, v2\.h\[2\]
+  dc:	7f72f020 	sqrdmlsh	h0, h1, v2\.h\[3\]
+  e0:	7f82f020 	sqrdmlsh	s0, s1, v2\.s\[0\]
+  e4:	7fa2f020 	sqrdmlsh	s0, s1, v2\.s\[1\]
+  e8:	7f82f820 	sqrdmlsh	s0, s1, v2\.s\[2\]
+  ec:	7fa2f820 	sqrdmlsh	s0, s1, v2\.s\[3\]
diff --git a/gas/testsuite/gas/aarch64/rdma.s b/gas/testsuite/gas/aarch64/rdma.s
new file mode 100644
index 0000000..7dbf914
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/rdma.s
@@ -0,0 +1,78 @@
+/* rdma.s Test file for AArch64 v8.1 Advanced-SIMD instructions.
+
+   Copyright (C) 2012-2015 Free Software Foundation, Inc.  Contributed by ARM Ltd.
+
+   This file is part of GAS.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the license, or
+   (at your option) any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; see the file COPYING3. If not,
+   see <http://www.gnu.org/licenses/>.  */
+
+
+	.text
+	.ifdef DIRECTIVE
+	.arch_extension rdma
+	.endif
+
+	.macro vect_inst I T
+	\I v0.\()\T, v1.\()\T, v2.\()\T
+	.endm
+
+	.text
+	.irp    inst, sqrdmlah, sqrdmlsh
+        .irp    type, 4h, 8h, 2s, 4s
+	vect_inst \inst \type
+        .endr
+	.endr
+
+	.macro scalar_inst I R
+	\I \R\()0, \R\()1, \R\()2
+	.endm
+
+	.text
+	.irp    inst, sqrdmlah, sqrdmlsh
+	.irp    reg, s,h
+	scalar_inst \inst \reg
+        .endr
+        .endr
+	
+	.macro vect_indexed_inst I S T N
+	\I v0.\S\T, v1.\S\T, v2.\T[\N]
+	.endm
+
+	.text
+	.irp    inst, sqrdmlah, sqrdmlsh
+	.irp    size, 4, 8
+	.irp    index 0,1,2,3
+	vect_indexed_inst \inst \size h \index
+        .endr
+	.endr
+	.irp    size, 2, 4
+	.irp    index 0,1,2,3
+	vect_indexed_inst \inst \size s \index
+        .endr
+	.endr
+	.endr
+	
+	.macro scalar_indexed_inst I T N
+	\I \T\()0, \T\()1, v2.\T[\N]
+	.endm
+
+	.text
+	.irp    inst, sqrdmlah, sqrdmlsh
+	.irp    type h,s
+	.irp    index 0,1,2,3
+	scalar_indexed_inst \inst \type \index
+	.endr
+	.endr
+	.endr