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[patch] Fix or1k gcc-4.9 -m32 compilation error
- From: Jan Kratochvil <jan dot kratochvil at redhat dot com>
- To: binutils at sourceware dot org
- Date: Mon, 9 Jun 2014 21:02:57 +0200
- Subject: [patch] Fix or1k gcc-4.9 -m32 compilation error
- Authentication-results: sourceware.org; auth=none
Hi,
Fedora Rawhide i686 (32-bit)
gcc-4.9.0-8.fc21.i686
libtool: compile: gcc -DHAVE_CONFIG_H -I. -I. -I. -I../bfd -I./../include -I./../bfd -W -Wall -Wstrict-prototypes -Wmissing-prototypes -Wshadow -Werror -g3 -pipe -Wall -fexceptions -fstack-protector-strong --param=ssp-buffer-size=4 -ftrack-macro-expansion=0 -fno-diagnostics-show-caret -fsanitize=address -MT or1k-asm.lo -MD -MP -MF .deps/or1k-asm.Tpo -c or1k-asm.c -o or1k-asm.o
In file included from or1k-asm.c:34:0:
or1k-desc.h:260:73: error: this decimal constant is unsigned only in ISO C90 [-Werror]
or1k-desc.h:263:73: error: this decimal constant is unsigned only in ISO C90 [-Werror]
or1k-desc.h:270:4: error: this decimal constant is unsigned only in ISO C90 [-Werror]
cc1: all warnings being treated as errors
make[4]: *** [or1k-asm.lo] Error 1
OK to check it in?
Thanks,
Jan
opcodes/
2014-06-09 Jan Kratochvil <jan.kratochvil@redhat.com>
* or1k-desc.h (SPR_FIELD_MASK_SYS_VR_VER, SPR_FIELD_MASK_SYS_UPR_CUP)
(SPR_FIELD_MASK_SYS_SR_CID): Add U suffix.
diff --git a/opcodes/or1k-desc.h b/opcodes/or1k-desc.h
index d27872f..1cf2a90 100644
--- a/opcodes/or1k-desc.h
+++ b/opcodes/or1k-desc.h
@@ -257,17 +257,17 @@ typedef enum spr_field_lsbs {
/* Enum declaration for SPR field masks. */
typedef enum spr_field_masks {
- SPR_FIELD_MASK_SYS_VR_REV = 63, SPR_FIELD_MASK_SYS_VR_CFG = 16711680, SPR_FIELD_MASK_SYS_VR_VER = 4278190080, SPR_FIELD_MASK_SYS_UPR_UP = 1
+ SPR_FIELD_MASK_SYS_VR_REV = 63, SPR_FIELD_MASK_SYS_VR_CFG = 16711680, SPR_FIELD_MASK_SYS_VR_VER = 4278190080U, SPR_FIELD_MASK_SYS_UPR_UP = 1
, SPR_FIELD_MASK_SYS_UPR_DCP = 2, SPR_FIELD_MASK_SYS_UPR_ICP = 4, SPR_FIELD_MASK_SYS_UPR_DMP = 8, SPR_FIELD_MASK_SYS_UPR_MP = 16
, SPR_FIELD_MASK_SYS_UPR_IMP = 32, SPR_FIELD_MASK_SYS_UPR_DUP = 64, SPR_FIELD_MASK_SYS_UPR_PCUP = 128, SPR_FIELD_MASK_SYS_UPR_PICP = 256
- , SPR_FIELD_MASK_SYS_UPR_PMP = 512, SPR_FIELD_MASK_SYS_UPR_TTP = 1024, SPR_FIELD_MASK_SYS_UPR_CUP = 4278190080, SPR_FIELD_MASK_SYS_CPUCFGR_NSGR = 15
+ , SPR_FIELD_MASK_SYS_UPR_PMP = 512, SPR_FIELD_MASK_SYS_UPR_TTP = 1024, SPR_FIELD_MASK_SYS_UPR_CUP = 4278190080U, SPR_FIELD_MASK_SYS_CPUCFGR_NSGR = 15
, SPR_FIELD_MASK_SYS_CPUCFGR_CGF = 16, SPR_FIELD_MASK_SYS_CPUCFGR_OB32S = 32, SPR_FIELD_MASK_SYS_CPUCFGR_OB64S = 64, SPR_FIELD_MASK_SYS_CPUCFGR_OF32S = 128
, SPR_FIELD_MASK_SYS_CPUCFGR_OF64S = 256, SPR_FIELD_MASK_SYS_CPUCFGR_OV64S = 512, SPR_FIELD_MASK_SYS_CPUCFGR_ND = 1024, SPR_FIELD_MASK_SYS_SR_SM = 1
, SPR_FIELD_MASK_SYS_SR_TEE = 2, SPR_FIELD_MASK_SYS_SR_IEE = 4, SPR_FIELD_MASK_SYS_SR_DCE = 8, SPR_FIELD_MASK_SYS_SR_ICE = 16
, SPR_FIELD_MASK_SYS_SR_DME = 32, SPR_FIELD_MASK_SYS_SR_IME = 64, SPR_FIELD_MASK_SYS_SR_LEE = 128, SPR_FIELD_MASK_SYS_SR_CE = 256
, SPR_FIELD_MASK_SYS_SR_F = 512, SPR_FIELD_MASK_SYS_SR_CY = 1024, SPR_FIELD_MASK_SYS_SR_OV = 2048, SPR_FIELD_MASK_SYS_SR_OVE = 4096
, SPR_FIELD_MASK_SYS_SR_DSX = 8192, SPR_FIELD_MASK_SYS_SR_EPH = 16384, SPR_FIELD_MASK_SYS_SR_FO = 32768, SPR_FIELD_MASK_SYS_SR_SUMRA = 65536
- , SPR_FIELD_MASK_SYS_SR_CID = 4026531840, SPR_FIELD_MASK_SYS_FPCSR_FPEE = 1, SPR_FIELD_MASK_SYS_FPCSR_RM = 6, SPR_FIELD_MASK_SYS_FPCSR_OVF = 8
+ , SPR_FIELD_MASK_SYS_SR_CID = 4026531840U, SPR_FIELD_MASK_SYS_FPCSR_FPEE = 1, SPR_FIELD_MASK_SYS_FPCSR_RM = 6, SPR_FIELD_MASK_SYS_FPCSR_OVF = 8
, SPR_FIELD_MASK_SYS_FPCSR_UNF = 16, SPR_FIELD_MASK_SYS_FPCSR_SNF = 32, SPR_FIELD_MASK_SYS_FPCSR_QNF = 64, SPR_FIELD_MASK_SYS_FPCSR_ZF = 128
, SPR_FIELD_MASK_SYS_FPCSR_IXF = 256, SPR_FIELD_MASK_SYS_FPCSR_IVF = 512, SPR_FIELD_MASK_SYS_FPCSR_INF = 1024, SPR_FIELD_MASK_SYS_FPCSR_DZF = 2048
} SPR_FIELD_MASKS;