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[PATCH] Fixing issue with "Rearrange MIPS INSN* masks" patch


The attached patch and ChangeLog fixes an issue with Mark Shinwell's 
"Rearrange MIPS INSN* masks" patch 
(  In the patch 
the pref instruction had its membership flags changed from I4|I32|G3 to
I4_32|G3.  Unfortunately G3 was defined as being I4, which made the actual
expanded flags as: I4|I32|I4 and therefore the membership flags should have
been I4_32.  Since the patch was committed G3 was redefined to be I4|EE.  My
fix just removes I4 from G3 making the expanded membership flags for pref as 

The patch and ChangeLog are below.

Ok to commit?

Many thanks,


Andrew Bennett
Software Design Engineer, MIPS Processor IP
Imagination Technologies Limited
t: +44 (0)113 2429814

2014-05-05  Andrew Bennett  <>

                * mips-opc.c (G3): Remove I4.

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 9181c3f..f3b287f 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -296,8 +296,7 @@ decode_mips_operand (const char *p)
#define G2      (T3             \

-#define G3      (I4             \
-                 |EE            \
+#define G3      (EE             \

 /* 64 bit CPU with 32 bit FPU (single float). */

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