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Re: glibc: loading of shared objects with holes wastes address space
Mathias Krause <firstname.lastname@example.org> writes:
> On Tue, Oct 18, 2011 at 3:44 PM, Ian Lance Taylor <email@example.com> wrote:
>> Mathias Krause <firstname.lastname@example.org> writes:
>>> I see. So the real problem are the holes themselves. If there wouldn't
>>> be any gap between two adjacent segments, then there would be no need
>>> to stuff them. And honestly, currently those holes are not needed at
>>> all. Neither the glibc nor the kernel seem to honor the alignment
>>> requirements when searching for a suitable address. So the question
>>> is: Why are the sections in the linker script aligned to MAXPAGESIZE
>>> instead of PAGESIZE, i.e. aligned to 2 MiB instead of 4 KiB? But it
>>> looks like this is more of a question for the binutils folks (CCed).
>> Because then the executable will still run on some hypothetical future
>> kernel that uses larger page sizes.
> Are there _any_ plans from Intel/AMD (or rumors, even) to drop the
> page size support for 4 KiB pages in a future x86-64 based
> architecture? At least, I'm not aware of such a thing. So this can not
> really be an argument for choosing 2 MiB for ELF segment alignment.
It's not the processor that matters here, it's the kernel. The question
is whether the kernel will want to some day require executables to use a
larger page size.