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[PATCH] MIPS/GAS/testsuite: Fine-grained MIPS FP ISA matching
- From: "Maciej W. Rozycki" <macro at codesourcery dot com>
- To: binutils at sourceware dot org
- Cc: Richard Sandiford <rdsandiford at googlemail dot com>
- Date: Wed, 10 Aug 2011 00:06:53 +0100 (BST)
- Subject: [PATCH] MIPS/GAS/testsuite: Fine-grained MIPS FP ISA matching
Hi,
While merging test suite changes I've noticed some recent 24K erratum
workaround cases have suboptimal coverage. Upon further investigation I
discovered we have no proper mechanism to depend on for FP ISA revisions
in multi-architecture tests. Therefore I decided to make one up.
The MIPS FP ISA evolved a bit differently to the integer ISA and the
dependencies are (roughly) as follows -- as far as the instruction set is
concerned:
1. MIPS I -- base FP instruction set (MIPS I FP ISA).
2. MIPS II -- 64-bit FP memory transfers, 32-bit fixed-point FP
instructions added (MIPS II FP ISA).
3. MIPS III -- 64-bit fixed-point FP instructions added (MIPS III FP ISA).
4. MIPS IV -- indexed FP memory transfers, FP multiply-accumulate,
reciprocal and conditional-move instructions added (MIPS IV
FP ISA).
5. MIPS V -- unaligned indexed FP memory transfers, paired-single FP
instructions added (MIPS V FP ISA).
Then MIPS architecture processors defined their FP ISAs as follows:
1. MIPS32 -- MIPS II FP ISA plus FP conditional-move instructions.
2. MIPS64 -- MIPS V FP ISA.
3. MIPS32r2 -- MIPS V FP ISA plus upper-half FP register transfers.
4. MIPS64r2 -- MIPS V FP ISA plus upper-half FP register transfers.
Therefore I propose to add a set of FP ISA properties as follows to let
test cases that include MIPS III, MIPS IV or MIPS V FP ISA instructions to
have better coverage. The change is imperfect as it doesn't cover MIPS32
ISA FP conditional-move instructions, but I think it is good enough
anyway, especially as I'm told original (r1) MIPS32 FP parts have never
been made. If someone needs to test such a combination, then they may
propose a further property to cover it (like with "ror", etc.).
With these bits in place, the change now extends the 24K erratum
workaround coverage to some older ISAs too. Ultimately, I think these
cases should be passed through microMIPS testing too, to make sure the
workaround is correctly disabled when assembling microMIPS code (there are
no 24K parts supporting the microMIPS ASE).
Comments?
2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
gas/testsuite/
* gas/mips/mips.exp: Define new "fpisa3", "fpisa4" and "fpisa5"
architecture properties adding them to "mips3", "mips4", "mips5"
and "mips32r2" architectures. Run the "24k-triple-stores-1"
test for "fpisa5" instead of "mips32r2". Run the
"24k-triple-stores-3" test for "mips2" instead of "mips3".
Maciej
binutils-24k-test-mips3.diff
Index: binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/mips.exp
===================================================================
--- binutils-fsf-trunk-quilt.orig/gas/testsuite/gas/mips/mips.exp 2011-08-09 00:57:25.000000000 +0100
+++ binutils-fsf-trunk-quilt/gas/testsuite/gas/mips/mips.exp 2011-08-09 23:08:44.000000000 +0100
@@ -55,6 +55,10 @@
# The architecture includes the instructions defined
# by that MIPS ISA.
#
+# fpisa3, fpisa4, fpisa5
+# The architecture includes the floating-point
+# instructions defined by that MIPS ISA.
+#
# gpr_ilocks
# The architecture interlocks GPRs accesses. (That is,
# there are no load delay slots.)
@@ -369,16 +373,16 @@ mips_arch_create mips1 32 {} {} \
{ -march=mips1 -mtune=mips1 } { -mmips:3000 }
mips_arch_create mips2 32 mips1 { gpr_ilocks } \
{ -march=mips2 -mtune=mips2 } { -mmips:6000 }
-mips_arch_create mips3 64 mips2 {} \
+mips_arch_create mips3 64 mips2 { fpisa3 } \
{ -march=mips3 -mtune=mips3 } { -mmips:4000 }
-mips_arch_create mips4 64 mips3 {} \
+mips_arch_create mips4 64 mips3 { fpisa4 } \
{ -march=mips4 -mtune=mips4 } { -mmips:8000 }
-mips_arch_create mips5 64 mips4 {} \
+mips_arch_create mips5 64 mips4 { fpisa5 } \
{ -march=mips5 -mtune=mips5 } { -mmips:mips5 }
mips_arch_create mips32 32 mips2 {} \
{ -march=mips32 -mtune=mips32 } { -mmips:isa32 } \
{ mipsisa32-*-* mipsisa32el-*-* }
-mips_arch_create mips32r2 32 mips32 { ror } \
+mips_arch_create mips32r2 32 mips32 { fpisa3 fpisa4 fpisa5 ror } \
{ -march=mips32r2 -mtune=mips32r2 } \
{ -mmips:isa32r2 } \
{ mipsisa32r2-*-* mipsisa32r2el-*-* }
@@ -492,11 +496,11 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "24k-branch-delay-1" \
[mips_arch_list_matching mips1 !micromips]
run_dump_test_arches "24k-triple-stores-1" \
- [mips_arch_list_matching mips32r2 !octeon !micromips]
+ [mips_arch_list_matching fpisa5 !octeon !micromips]
run_dump_test_arches "24k-triple-stores-2" \
[mips_arch_list_matching mips2 !micromips]
run_dump_test_arches "24k-triple-stores-3" \
- [mips_arch_list_matching mips3 !micromips]
+ [mips_arch_list_matching mips2 !micromips]
run_dump_test_arches "24k-triple-stores-4" \
[mips_arch_list_matching mips2 !micromips]
run_dump_test_arches "24k-triple-stores-5" \