This is the mail archive of the
binutils@sources.redhat.com
mailing list for the binutils project.
[PATCH] Support for MIPS16 HI16/LO16 relocations
- From: "Maciej W. Rozycki" <macro at mips dot com>
- To: binutils at sources dot redhat dot com
- Cc: Nigel Stephens <nigel at mips dot com>, "Maciej W. Rozycki" <macro at linux-mips dot org>
- Date: Tue, 15 Feb 2005 17:09:05 +0000 (GMT)
- Subject: [PATCH] Support for MIPS16 HI16/LO16 relocations
Hello,
Here is a set of changes that we've developed to add support for MIPS16
HI16 and LO16 relocations. Their semantics is exactly the same as that of
their standard MIPS ABI counterparts, except due to the format of opcodes
used addends are scrambled in binaries, like for MIPS16 GPREL relocations.
As the number of MIPS16 relocations supported has grown, we've grouped
their howtos into separate tables for unified handling, fixing RELA
support on the way. We've added two separate functions to perform bit
shuffling, which has allowed us to unify some code and use generic
functions for addend calculation.
We have also added a second table for percent operators, which
incorporates the existing %gprel one as well as new %hi and %lo ones.
They are chosen appropriately by parse_relocation() based on the
mips/mips16 assembly mode in effect.
For binary compatibility with our SDE 5 toolchain the patch reserves two
codes for MIPS16 GOT16 and CALL16 relocation. We hope that is not a
problem -- we plan to submit code to handle them as soon as we have MIPS16
PIC support ported to current binutils.
A new testcase is included covering both gas and ld (the latter being
somewhat inadequately tested for MIPS16 in general). Only (o)32 and n32
ABIs are tested, though, as the lack of HIGHER and HIGHEST relocations
makes (n)64 tests a bit pointless. We do not expect a high demand for
these (n)64 relocations, but we consider adding them anyway for
completeness.
Binutils have been built with the changes applied and tested for
mips64-linux-gnu, mipsel-linux-gnu and mips64el-elf with no regressions.
bfd/:
2005-02-15 Nigel Stephens <nigel@mips.com>
Maciej W. Rozycki <macro@mips.com>
* elf32-mips.c (elf_mips16_howto_table_rel): New array for MIPS16
reloc howtos. Add R_MIPS16_HI16 and R_MIPS16_LO16 relocs and
R_MIPS16_GOT16 and R_MIPS16_CALL16 placeholders.
(elf_mips16_jump_howto): Move into elf_mips16_howto_table_rel.
(elf_mips16_gprel_howto): Likewise. Redefine src_mask and
dst_mask.
(mips16_gprel_reloc): Remove bit shuffling; call
_bfd_mips16_elf_reloc_unshuffle(), _bfd_mips_elf_gprel16_with_gp()
and _bfd_mips16_elf_reloc_shuffle() instead.
(mips16_reloc_map): New reloc map for MIPS16 relocs.
(bfd_elf32_bfd_reloc_type_lookup): Use mips16_reloc_map for MIPS16
relocs.
(mips_elf32_rtype_to_howto): Fetch MIPS16 howtos from
elf_mips16_howto_table_rel.
* elf64-mips.c (mips16_elf64_howto_table_rel): New array for
MIPS16 REL reloc howtos. Add R_MIPS16_HI16 and R_MIPS16_LO16
relocs and R_MIPS16_GOT16 and R_MIPS16_CALL16 placeholders.
(elf_mips16_jump_howto): Move into mips16_elf64_howto_table_rel.
(elf_mips16_gprel_howto): Likewise. Redefine src_mask and
dst_mask.
(mips16_elf64_howto_table_rela): New array for MIPS16 RELA
reloc howtos. Add R_MIPS16_26, R_MIPS16_GPREL, R_MIPS16_HI16 and
R_MIPS16_LO16 relocs and R_MIPS16_GOT16 and R_MIPS16_CALL16
placeholders.
(mips16_gprel_reloc): Remove bit shuffling; call
_bfd_mips16_elf_reloc_unshuffle(), _bfd_mips_elf_gprel16_with_gp()
and _bfd_mips16_elf_reloc_shuffle() instead.
(mips16_reloc_map): New reloc map for MIPS16 relocs.
(bfd_elf64_bfd_reloc_type_lookup): Use mips16_reloc_map for MIPS16
relocs.
(mips_elf64_rtype_to_howto): Fetch MIPS16 howtos from
mips16_elf64_howto_table_rela or mips16_elf64_howto_table_rel.
* elfn32-mips.c (elf_mips16_howto_table_rel): New array for MIPS16
REL reloc howtos. Add R_MIPS16_HI16 and R_MIPS16_LO16 relocs and
R_MIPS16_GOT16 and R_MIPS16_CALL16 placeholders.
(elf_mips16_jump_howto): Move into elf_mips16_howto_table_rel.
(elf_mips16_gprel_howto): Likewise. Redefine src_mask and
dst_mask.
(mips16_gprel_reloc): Remove bit shuffling; call
_bfd_mips16_elf_reloc_unshuffle(), _bfd_mips_elf_gprel16_with_gp()
and _bfd_mips16_elf_reloc_shuffle() instead.
(mips16_reloc_map): New reloc map for MIPS16 relocs.
(bfd_elf32_bfd_reloc_type_lookup): Use mips16_reloc_map for MIPS16
relocs.
(mips_elf_n32_rtype_to_howto): Fetch MIPS16 howtos from
elf_mips16_howto_table_rela or elf_mips16_howto_table_rel.
* elfxx-mips.c (_bfd_mips16_elf_reloc_unshuffle): New function to
handle bit shuffling for MIPS16 relocs.
(_bfd_mips16_elf_reloc_shuffle): Likewise.
(_bfd_mips_elf_lo16_reloc): Use _bfd_mips16_elf_reloc_unshuffle()
and _bfd_mips16_elf_reloc_shuffle().
(_bfd_mips_elf_generic_reloc): Likewise.
(mips_elf_calculate_relocation): Likewise. Handle R_MIPS16_HI16
and R_MIPS16_LO16.
(mips_elf_obtain_contents): Remove bit shuffling.
(mips_elf_perform_relocation): Likewise; call
_bfd_mips16_elf_reloc_unshuffle() and _bfd_mips16_elf_reloc_shuffle()
instead.
(_bfd_mips_elf_relocate_section): Likewise. Handle R_MIPS16_HI16
and R_MIPS16_LO16.
* elfxx-mips.h (_bfd_mips16_elf_reloc_unshuffle): Declare.
(_bfd_mips16_elf_reloc_shuffle): Likewise.
* reloc.c (BFD_RELOC_MIPS16_HI16): New reloc.
(BFD_RELOC_MIPS16_HI16_S): Likewise.
(BFD_RELOC_MIPS16_LO16): Likewise.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/:
2005-02-15 Nigel Stephens <nigel@mips.com>
Maciej W. Rozycki <macro@mips.com>
* config/tc-mips.c (reloc_needs_lo_p): Handle
BFD_RELOC_MIPS16_HI16_S.
(fixup_has_matching_lo_p): Handle BFD_RELOC_MIPS16_LO16.
(append_insn): Add BFD_RELOC_MIPS16_GPREL, BFD_RELOC_MIPS16_HI16_S
and BFD_RELOC_MIPS16_LO16 to relocs to suppress overflow
complaints on.
(mips16_ip): Resolve BFD_RELOC_MIPS16_HI16_S,
BFD_RELOC_MIPS16_HI16 and BFD_RELOC_MIPS16_LO16 for constants.
Call my_getSmallExpression() to parse percent operators.
(percent_op_match, mips_percent_op): Separate definitions.
(mips16_percent_op): Define percent operators for the MIPS16 mode.
(parse_relocation): Handle the MIPS16 mode using
mips16_percent_op.
(md_apply_fix3): Handle BFD_RELOC_MIPS16_HI16,
BFD_RELOC_MIPS16_HI16_S and BFD_RELOC_MIPS16_LO16.
gas/testsuite/:
2005-02-15 Nigel Stephens <nigel@mips.com>
Maciej W. Rozycki <macro@mips.com>
* gas/mips/mips16-hilo.d: New test for the R_MIPS16_HI16 and
R_MIPS16_LO16 relocs.
* gas/mips/mips16-hilo-n32.d: Likewise, for the n32 ABI.
* gas/mips/mips16-hilo.s: Source for the new tests.
* gas/mips/mips.exp: Run the new tests.
include/:
2005-02-15 Nigel Stephens <nigel@mips.com>
Maciej W. Rozycki <macro@mips.com>
* elf/mips.h (R_MIPS16_GOT16): New reloc code.
(R_MIPS16_CALL16): Likewise.
(R_MIPS16_HI16): Likewise.
(R_MIPS16_LO16): Likewise.
(R_MIPS16_min): New fake reloc code.
(R_MIPS16_max): Likewise.
ld/testsuite/:
2005-02-15 Nigel Stephens <nigel@mips.com>
Maciej W. Rozycki <macro@mips.com>
* ld-mips-elf/mips16-hilo.d: New test for the R_MIPS16_HI16 and
R_MIPS16_LO16 relocs.
* ld-mips-elf/mips16-hilo-n32.d: Likewise, for the n32 ABI.
* ld-mips-elf/mips16-hilo.s: Auxiliary source for the new tests.
* ld-mips-elf/mips-elf.exp: Run the new tests.
OK to apply?
Maciej
binutils-2.15.94-20050214-mips16-hilo.patch
diff -up --recursive --new-file binutils-2.15.94-20050214.macro/bfd/bfd-in2.h binutils-2.15.94-20050214/bfd/bfd-in2.h
--- binutils-2.15.94-20050214.macro/bfd/bfd-in2.h 2005-02-14 11:39:59.000000000 +0000
+++ binutils-2.15.94-20050214/bfd/bfd-in2.h 2005-02-14 11:44:27.000000000 +0000
@@ -2354,6 +2354,18 @@ to compensate for the borrow when the lo
/* Low 16 bits. */
BFD_RELOC_LO16,
+/* MIPS16 high 16 bits of 32-bit value. */
+ BFD_RELOC_MIPS16_HI16,
+
+/* MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
+extended and added to form the final result. If the low 16
+bits form a negative number, we need to add one to the high value
+to compensate for the borrow when the low bits are added. */
+ BFD_RELOC_MIPS16_HI16_S,
+
+/* MIPS16 low 16 bits. */
+ BFD_RELOC_MIPS16_LO16,
+
/* Relocation against a MIPS literal section. */
BFD_RELOC_MIPS_LITERAL,
diff -up --recursive --new-file binutils-2.15.94-20050214.macro/bfd/elf32-mips.c binutils-2.15.94-20050214/bfd/elf32-mips.c
--- binutils-2.15.94-20050214.macro/bfd/elf32-mips.c 2005-02-14 11:40:01.000000000 +0000
+++ binutils-2.15.94-20050214/bfd/elf32-mips.c 2005-02-14 11:44:27.000000000 +0000
@@ -564,8 +564,9 @@ static reloc_howto_type elf_mips_ctor64_
0xffffffff, /* dst_mask */
FALSE); /* pcrel_offset */
-/* The reloc used for the mips16 jump instruction. */
-static reloc_howto_type elf_mips16_jump_howto =
+static reloc_howto_type elf_mips16_howto_table_rel[] =
+{
+ /* The reloc used for the mips16 jump instruction. */
HOWTO (R_MIPS16_26, /* type */
2, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
@@ -581,10 +582,9 @@ static reloc_howto_type elf_mips16_jump_
TRUE, /* partial_inplace */
0x3ffffff, /* src_mask */
0x3ffffff, /* dst_mask */
- FALSE); /* pcrel_offset */
+ FALSE), /* pcrel_offset */
-/* The reloc used for the mips16 gprel instruction. */
-static reloc_howto_type elf_mips16_gprel_howto =
+ /* The reloc used for the mips16 gprel instruction. */
HOWTO (R_MIPS16_GPREL, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
@@ -595,9 +595,46 @@ static reloc_howto_type elf_mips16_gprel
mips16_gprel_reloc, /* special_function */
"R_MIPS16_GPREL", /* name */
TRUE, /* partial_inplace */
- 0x07ff001f, /* src_mask */
- 0x07ff001f, /* dst_mask */
- FALSE); /* pcrel_offset */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* A placeholder for MIPS16 reference to global offset table. */
+ EMPTY_HOWTO (R_MIPS16_GOT16),
+
+ /* A placeholder for MIPS16 16 bit call through global offset table. */
+ EMPTY_HOWTO (R_MIPS16_CALL16),
+
+ /* MIPS16 high 16 bits of symbol value. */
+ HOWTO (R_MIPS16_HI16, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_hi16_reloc, /* special_function */
+ "R_MIPS16_HI16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* MIPS16 low 16 bits of symbol value. */
+ HOWTO (R_MIPS16_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_lo16_reloc, /* special_function */
+ "R_MIPS16_LO16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+};
/* 16 bit offset for pc-relative branches. */
static reloc_howto_type elf_mips_gnu_rel16_s2 =
@@ -957,11 +994,8 @@ mips16_gprel_reloc (bfd *abfd, arelent *
{
bfd_boolean relocatable;
bfd_reloc_status_type ret;
+ bfd_byte *location;
bfd_vma gp;
- unsigned short extend = 0;
- unsigned short insn = 0;
- bfd_signed_vma val;
- bfd_vma relocation;
/* If we're relocating, and this is an external symbol, we don't want
to change anything. */
@@ -986,55 +1020,16 @@ mips16_gprel_reloc (bfd *abfd, arelent *
if (ret != bfd_reloc_ok)
return ret;
- if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
- return bfd_reloc_outofrange;
+ location = (bfd_byte *) data + reloc_entry->address;
+ _bfd_mips16_elf_reloc_unshuffle (abfd, reloc_entry->howto->type, FALSE,
+ location);
+ ret = _bfd_mips_elf_gprel16_with_gp (abfd, symbol, reloc_entry,
+ input_section, relocatable,
+ data, gp);
+ _bfd_mips16_elf_reloc_shuffle (abfd, reloc_entry->howto->type, !relocatable,
+ location);
- if (bfd_is_com_section (symbol->section))
- relocation = 0;
- else
- relocation = symbol->value;
-
- relocation += symbol->section->output_section->vma;
- relocation += symbol->section->output_offset;
-
- /* Set val to the offset into the section or symbol. */
- val = reloc_entry->addend;
-
- if (reloc_entry->howto->partial_inplace)
- {
- /* Pick up the mips16 extend instruction and the real instruction. */
- extend = bfd_get_16 (abfd, (bfd_byte *) data + reloc_entry->address);
- insn = bfd_get_16 (abfd, (bfd_byte *) data + reloc_entry->address + 2);
- val += ((extend & 0x1f) << 11) | (extend & 0x7e0) | (insn & 0x1f);
- }
-
- _bfd_mips_elf_sign_extend(val, 16);
-
- /* Adjust val for the final section location and GP value. If we
- are producing relocatable output, we don't want to do this for
- an external symbol. */
- if (! relocatable
- || (symbol->flags & BSF_SECTION_SYM) != 0)
- val += relocation - gp;
-
- if (reloc_entry->howto->partial_inplace)
- {
- bfd_put_16 (abfd,
- (extend & 0xf800) | ((val >> 11) & 0x1f) | (val & 0x7e0),
- (bfd_byte *) data + reloc_entry->address);
- bfd_put_16 (abfd,
- (insn & 0xffe0) | (val & 0x1f),
- (bfd_byte *) data + reloc_entry->address + 2);
- }
- else
- reloc_entry->addend = val;
-
- if (relocatable)
- reloc_entry->address += input_section->output_offset;
- else if (((val & ~0xffff) != ~0xffff) && ((val & ~0xffff) != 0))
- return bfd_reloc_overflow;
-
- return bfd_reloc_ok;
+ return ret;
}
/* A mapping from BFD reloc types to MIPS ELF reloc types. */
@@ -1070,6 +1065,14 @@ static const struct elf_reloc_map mips_r
{ BFD_RELOC_MIPS_GOT_DISP, R_MIPS_GOT_DISP }
};
+static const struct elf_reloc_map mips16_reloc_map[] =
+{
+ { BFD_RELOC_MIPS16_JMP, R_MIPS16_26 - R_MIPS16_min },
+ { BFD_RELOC_MIPS16_GPREL, R_MIPS16_GPREL - R_MIPS16_min },
+ { BFD_RELOC_MIPS16_HI16_S, R_MIPS16_HI16 - R_MIPS16_min },
+ { BFD_RELOC_MIPS16_LO16, R_MIPS16_LO16 - R_MIPS16_min },
+};
+
/* Given a BFD reloc type, return a howto structure. */
static reloc_howto_type *
@@ -1077,6 +1080,7 @@ bfd_elf32_bfd_reloc_type_lookup (bfd *ab
{
unsigned int i;
reloc_howto_type *howto_table = elf_mips_howto_table_rel;
+ reloc_howto_type *howto16_table = elf_mips16_howto_table_rel;
for (i = 0; i < sizeof (mips_reloc_map) / sizeof (struct elf_reloc_map);
i++)
@@ -1085,6 +1089,13 @@ bfd_elf32_bfd_reloc_type_lookup (bfd *ab
return &howto_table[(int) mips_reloc_map[i].elf_val];
}
+ for (i = 0; i < sizeof (mips16_reloc_map) / sizeof (struct elf_reloc_map);
+ i++)
+ {
+ if (mips16_reloc_map[i].bfd_val == code)
+ return &howto16_table[(int) mips16_reloc_map[i].elf_val];
+ }
+
switch (code)
{
default:
@@ -1101,10 +1112,6 @@ bfd_elf32_bfd_reloc_type_lookup (bfd *ab
else
return &howto_table[(int) R_MIPS_32];
- case BFD_RELOC_MIPS16_JMP:
- return &elf_mips16_jump_howto;
- case BFD_RELOC_MIPS16_GPREL:
- return &elf_mips16_gprel_howto;
case BFD_RELOC_VTABLE_INHERIT:
return &elf_mips_gnu_vtinherit_howto;
case BFD_RELOC_VTABLE_ENTRY:
@@ -1124,10 +1131,6 @@ mips_elf32_rtype_to_howto (unsigned int
{
switch (r_type)
{
- case R_MIPS16_26:
- return &elf_mips16_jump_howto;
- case R_MIPS16_GPREL:
- return &elf_mips16_gprel_howto;
case R_MIPS_GNU_VTINHERIT:
return &elf_mips_gnu_vtinherit_howto;
case R_MIPS_GNU_VTENTRY:
@@ -1137,6 +1140,8 @@ mips_elf32_rtype_to_howto (unsigned int
case R_MIPS_PC32:
return &elf_mips_gnu_pcrel32;
default:
+ if (r_type >= R_MIPS16_min && r_type < R_MIPS16_max)
+ return &elf_mips16_howto_table_rel[r_type - R_MIPS16_min];
BFD_ASSERT (r_type < (unsigned int) R_MIPS_max);
return &elf_mips_howto_table_rel[r_type];
}
diff -up --recursive --new-file binutils-2.15.94-20050214.macro/bfd/elf64-mips.c binutils-2.15.94-20050214/bfd/elf64-mips.c
--- binutils-2.15.94-20050214.macro/bfd/elf64-mips.c 2005-02-14 11:40:01.000000000 +0000
+++ binutils-2.15.94-20050214/bfd/elf64-mips.c 2005-02-14 11:46:26.000000000 +0000
@@ -1153,8 +1153,9 @@ static reloc_howto_type mips_elf64_howto
FALSE), /* pcrel_offset */
};
-/* The reloc used for the mips16 jump instruction. */
-static reloc_howto_type elf_mips16_jump_howto =
+static reloc_howto_type mips16_elf64_howto_table_rel[] =
+{
+ /* The reloc used for the mips16 jump instruction. */
HOWTO (R_MIPS16_26, /* type */
2, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
@@ -1170,10 +1171,9 @@ static reloc_howto_type elf_mips16_jump_
TRUE, /* partial_inplace */
0x3ffffff, /* src_mask */
0x3ffffff, /* dst_mask */
- FALSE); /* pcrel_offset */
+ FALSE), /* pcrel_offset */
-/* The reloc used for the mips16 gprel instruction. */
-static reloc_howto_type elf_mips16_gprel_howto =
+ /* The reloc used for the mips16 gprel instruction. */
HOWTO (R_MIPS16_GPREL, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
@@ -1184,9 +1184,118 @@ static reloc_howto_type elf_mips16_gprel
mips16_gprel_reloc, /* special_function */
"R_MIPS16_GPREL", /* name */
TRUE, /* partial_inplace */
- 0x07ff001f, /* src_mask */
- 0x07ff001f, /* dst_mask */
- FALSE); /* pcrel_offset */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* A placeholder for MIPS16 reference to global offset table. */
+ EMPTY_HOWTO (R_MIPS16_GOT16),
+
+ /* A placeholder for MIPS16 16 bit call through global offset table. */
+ EMPTY_HOWTO (R_MIPS16_CALL16),
+
+ /* MIPS16 high 16 bits of symbol value. */
+ HOWTO (R_MIPS16_HI16, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_hi16_reloc, /* special_function */
+ "R_MIPS16_HI16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* MIPS16 low 16 bits of symbol value. */
+ HOWTO (R_MIPS16_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_lo16_reloc, /* special_function */
+ "R_MIPS16_LO16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+};
+
+static reloc_howto_type mips16_elf64_howto_table_rela[] =
+{
+ /* The reloc used for the mips16 jump instruction. */
+ HOWTO (R_MIPS16_26, /* type */
+ 2, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 26, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ /* This needs complex overflow
+ detection, because the upper four
+ bits must match the PC. */
+ mips16_jump_reloc, /* special_function */
+ "R_MIPS16_26", /* name */
+ FALSE, /* partial_inplace */
+ 0x3ffffff, /* src_mask */
+ 0x3ffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* The reloc used for the mips16 gprel instruction. */
+ HOWTO (R_MIPS16_GPREL, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ mips16_gprel_reloc, /* special_function */
+ "R_MIPS16_GPREL", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* A placeholder for MIPS16 reference to global offset table. */
+ EMPTY_HOWTO (R_MIPS16_GOT16),
+
+ /* A placeholder for MIPS16 16 bit call through global offset table. */
+ EMPTY_HOWTO (R_MIPS16_CALL16),
+
+ /* MIPS16 high 16 bits of symbol value. */
+ HOWTO (R_MIPS16_HI16, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_hi16_reloc, /* special_function */
+ "R_MIPS16_HI16", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* MIPS16 low 16 bits of symbol value. */
+ HOWTO (R_MIPS16_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_lo16_reloc, /* special_function */
+ "R_MIPS16_LO16", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+};
/* GNU extension to record C++ vtable hierarchy */
static reloc_howto_type elf_mips_gnu_vtinherit_howto =
@@ -1703,11 +1812,8 @@ mips16_gprel_reloc (bfd *abfd, arelent *
{
bfd_boolean relocatable;
bfd_reloc_status_type ret;
+ bfd_byte *location;
bfd_vma gp;
- unsigned short extend = 0;
- unsigned short insn = 0;
- bfd_signed_vma val;
- bfd_vma relocation;
/* If we're relocating, and this is an external symbol, we don't want
to change anything. */
@@ -1732,55 +1838,16 @@ mips16_gprel_reloc (bfd *abfd, arelent *
if (ret != bfd_reloc_ok)
return ret;
- if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
- return bfd_reloc_outofrange;
-
- if (bfd_is_com_section (symbol->section))
- relocation = 0;
- else
- relocation = symbol->value;
-
- relocation += symbol->section->output_section->vma;
- relocation += symbol->section->output_offset;
-
- /* Set val to the offset into the section or symbol. */
- val = reloc_entry->addend;
-
- if (reloc_entry->howto->partial_inplace)
- {
- /* Pick up the mips16 extend instruction and the real instruction. */
- extend = bfd_get_16 (abfd, (bfd_byte *) data + reloc_entry->address);
- insn = bfd_get_16 (abfd, (bfd_byte *) data + reloc_entry->address + 2);
- val += ((extend & 0x1f) << 11) | (extend & 0x7e0) | (insn & 0x1f);
- }
-
- _bfd_mips_elf_sign_extend(val, 16);
+ location = (bfd_byte *) data + reloc_entry->address;
+ _bfd_mips16_elf_reloc_unshuffle (abfd, reloc_entry->howto->type, FALSE,
+ location);
+ ret = _bfd_mips_elf_gprel16_with_gp (abfd, symbol, reloc_entry,
+ input_section, relocatable,
+ data, gp);
+ _bfd_mips16_elf_reloc_shuffle (abfd, reloc_entry->howto->type, !relocatable,
+ location);
- /* Adjust val for the final section location and GP value. If we
- are producing relocatable output, we don't want to do this for
- an external symbol. */
- if (! relocatable
- || (symbol->flags & BSF_SECTION_SYM) != 0)
- val += relocation - gp;
-
- if (reloc_entry->howto->partial_inplace)
- {
- bfd_put_16 (abfd,
- (extend & 0xf800) | ((val >> 11) & 0x1f) | (val & 0x7e0),
- (bfd_byte *) data + reloc_entry->address);
- bfd_put_16 (abfd,
- (insn & 0xffe0) | (val & 0x1f),
- (bfd_byte *) data + reloc_entry->address + 2);
- }
- else
- reloc_entry->addend = val;
-
- if (relocatable)
- reloc_entry->address += input_section->output_offset;
- else if (((val & ~0xffff) != ~0xffff) && ((val & ~0xffff) != 0))
- return bfd_reloc_overflow;
-
- return bfd_reloc_ok;
+ return ret;
}
/* A mapping from BFD reloc types to MIPS ELF reloc types. */
@@ -1829,6 +1896,14 @@ static const struct elf_reloc_map mips_r
{ BFD_RELOC_MIPS_JALR, R_MIPS_JALR }
};
+static const struct elf_reloc_map mips16_reloc_map[] =
+{
+ { BFD_RELOC_MIPS16_JMP, R_MIPS16_26 - R_MIPS16_min },
+ { BFD_RELOC_MIPS16_GPREL, R_MIPS16_GPREL - R_MIPS16_min },
+ { BFD_RELOC_MIPS16_HI16_S, R_MIPS16_HI16 - R_MIPS16_min },
+ { BFD_RELOC_MIPS16_LO16, R_MIPS16_LO16 - R_MIPS16_min },
+};
+
/* Given a BFD reloc type, return a howto structure. */
static reloc_howto_type *
@@ -1839,6 +1914,7 @@ bfd_elf64_bfd_reloc_type_lookup (bfd *ab
/* FIXME: We default to RELA here instead of choosing the right
relocation variant. */
reloc_howto_type *howto_table = mips_elf64_howto_table_rela;
+ reloc_howto_type *howto16_table = mips16_elf64_howto_table_rela;
for (i = 0; i < sizeof (mips_reloc_map) / sizeof (struct elf_reloc_map);
i++)
@@ -1847,12 +1923,15 @@ bfd_elf64_bfd_reloc_type_lookup (bfd *ab
return &howto_table[(int) mips_reloc_map[i].elf_val];
}
+ for (i = 0; i < sizeof (mips16_reloc_map) / sizeof (struct elf_reloc_map);
+ i++)
+ {
+ if (mips16_reloc_map[i].bfd_val == code)
+ return &howto16_table[(int) mips16_reloc_map[i].elf_val];
+ }
+
switch (code)
{
- case BFD_RELOC_MIPS16_JMP:
- return &elf_mips16_jump_howto;
- case BFD_RELOC_MIPS16_GPREL:
- return &elf_mips16_gprel_howto;
case BFD_RELOC_VTABLE_INHERIT:
return &elf_mips_gnu_vtinherit_howto;
case BFD_RELOC_VTABLE_ENTRY:
@@ -1872,10 +1951,6 @@ mips_elf64_rtype_to_howto (unsigned int
{
switch (r_type)
{
- case R_MIPS16_26:
- return &elf_mips16_jump_howto;
- case R_MIPS16_GPREL:
- return &elf_mips16_gprel_howto;
case R_MIPS_GNU_VTINHERIT:
return &elf_mips_gnu_vtinherit_howto;
case R_MIPS_GNU_VTENTRY:
@@ -1886,6 +1961,13 @@ mips_elf64_rtype_to_howto (unsigned int
else
return &elf_mips_gnu_rel16_s2;
default:
+ if (r_type >= R_MIPS16_min && r_type < R_MIPS16_max)
+ {
+ if (rela_p)
+ return &mips16_elf64_howto_table_rela[r_type - R_MIPS16_min];
+ else
+ return &mips16_elf64_howto_table_rel[r_type - R_MIPS16_min];
+ }
BFD_ASSERT (r_type < (unsigned int) R_MIPS_max);
if (rela_p)
return &mips_elf64_howto_table_rela[r_type];
diff -up --recursive --new-file binutils-2.15.94-20050214.macro/bfd/elfn32-mips.c binutils-2.15.94-20050214/bfd/elfn32-mips.c
--- binutils-2.15.94-20050214.macro/bfd/elfn32-mips.c 2005-02-14 11:40:02.000000000 +0000
+++ binutils-2.15.94-20050214/bfd/elfn32-mips.c 2005-02-14 11:44:27.000000000 +0000
@@ -1119,8 +1119,9 @@ static reloc_howto_type elf_mips_howto_t
FALSE), /* pcrel_offset */
};
-/* The reloc used for the mips16 jump instruction. */
-static reloc_howto_type elf_mips16_jump_howto =
+static reloc_howto_type elf_mips16_howto_table_rel[] =
+{
+ /* The reloc used for the mips16 jump instruction. */
HOWTO (R_MIPS16_26, /* type */
2, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
@@ -1136,10 +1137,9 @@ static reloc_howto_type elf_mips16_jump_
TRUE, /* partial_inplace */
0x3ffffff, /* src_mask */
0x3ffffff, /* dst_mask */
- FALSE); /* pcrel_offset */
+ FALSE), /* pcrel_offset */
-/* The reloc used for the mips16 gprel instruction. */
-static reloc_howto_type elf_mips16_gprel_howto =
+ /* The reloc used for the mips16 gprel instruction. */
HOWTO (R_MIPS16_GPREL, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
@@ -1150,9 +1150,118 @@ static reloc_howto_type elf_mips16_gprel
mips16_gprel_reloc, /* special_function */
"R_MIPS16_GPREL", /* name */
TRUE, /* partial_inplace */
- 0x07ff001f, /* src_mask */
- 0x07ff001f, /* dst_mask */
- FALSE); /* pcrel_offset */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* A placeholder for MIPS16 reference to global offset table. */
+ EMPTY_HOWTO (R_MIPS16_GOT16),
+
+ /* A placeholder for MIPS16 16 bit call through global offset table. */
+ EMPTY_HOWTO (R_MIPS16_CALL16),
+
+ /* MIPS16 high 16 bits of symbol value. */
+ HOWTO (R_MIPS16_HI16, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_hi16_reloc, /* special_function */
+ "R_MIPS16_HI16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* MIPS16 low 16 bits of symbol value. */
+ HOWTO (R_MIPS16_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_lo16_reloc, /* special_function */
+ "R_MIPS16_LO16", /* name */
+ TRUE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+};
+
+static reloc_howto_type elf_mips16_howto_table_rela[] =
+{
+ /* The reloc used for the mips16 jump instruction. */
+ HOWTO (R_MIPS16_26, /* type */
+ 2, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 26, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ /* This needs complex overflow
+ detection, because the upper four
+ bits must match the PC. */
+ mips16_jump_reloc, /* special_function */
+ "R_MIPS16_26", /* name */
+ FALSE, /* partial_inplace */
+ 0x3ffffff, /* src_mask */
+ 0x3ffffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* The reloc used for the mips16 gprel instruction. */
+ HOWTO (R_MIPS16_GPREL, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_signed, /* complain_on_overflow */
+ mips16_gprel_reloc, /* special_function */
+ "R_MIPS16_GPREL", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* A placeholder for MIPS16 reference to global offset table. */
+ EMPTY_HOWTO (R_MIPS16_GOT16),
+
+ /* A placeholder for MIPS16 16 bit call through global offset table. */
+ EMPTY_HOWTO (R_MIPS16_CALL16),
+
+ /* MIPS16 high 16 bits of symbol value. */
+ HOWTO (R_MIPS16_HI16, /* type */
+ 16, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_hi16_reloc, /* special_function */
+ "R_MIPS16_HI16", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+
+ /* MIPS16 low 16 bits of symbol value. */
+ HOWTO (R_MIPS16_LO16, /* type */
+ 0, /* rightshift */
+ 2, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_dont, /* complain_on_overflow */
+ _bfd_mips_elf_lo16_reloc, /* special_function */
+ "R_MIPS16_LO16", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
+};
/* GNU extension to record C++ vtable hierarchy */
static reloc_howto_type elf_mips_gnu_vtinherit_howto =
@@ -1511,11 +1620,8 @@ mips16_gprel_reloc (bfd *abfd, arelent *
{
bfd_boolean relocatable;
bfd_reloc_status_type ret;
+ bfd_byte *location;
bfd_vma gp;
- unsigned short extend = 0;
- unsigned short insn = 0;
- bfd_signed_vma val;
- bfd_vma relocation;
/* If we're relocating, and this is an external symbol, we don't want
to change anything. */
@@ -1540,55 +1646,16 @@ mips16_gprel_reloc (bfd *abfd, arelent *
if (ret != bfd_reloc_ok)
return ret;
- if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
- return bfd_reloc_outofrange;
-
- if (bfd_is_com_section (symbol->section))
- relocation = 0;
- else
- relocation = symbol->value;
-
- relocation += symbol->section->output_section->vma;
- relocation += symbol->section->output_offset;
-
- /* Set val to the offset into the section or symbol. */
- val = reloc_entry->addend;
-
- if (reloc_entry->howto->partial_inplace)
- {
- /* Pick up the mips16 extend instruction and the real instruction. */
- extend = bfd_get_16 (abfd, (bfd_byte *) data + reloc_entry->address);
- insn = bfd_get_16 (abfd, (bfd_byte *) data + reloc_entry->address + 2);
- val += ((extend & 0x1f) << 11) | (extend & 0x7e0) | (insn & 0x1f);
- }
-
- _bfd_mips_elf_sign_extend(val, 16);
-
- /* Adjust val for the final section location and GP value. If we
- are producing relocatable output, we don't want to do this for
- an external symbol. */
- if (! relocatable
- || (symbol->flags & BSF_SECTION_SYM) != 0)
- val += relocation - gp;
-
- if (reloc_entry->howto->partial_inplace)
- {
- bfd_put_16 (abfd,
- (extend & 0xf800) | ((val >> 11) & 0x1f) | (val & 0x7e0),
- (bfd_byte *) data + reloc_entry->address);
- bfd_put_16 (abfd,
- (insn & 0xffe0) | (val & 0x1f),
- (bfd_byte *) data + reloc_entry->address + 2);
- }
- else
- reloc_entry->addend = val;
-
- if (relocatable)
- reloc_entry->address += input_section->output_offset;
- else if (((val & ~0xffff) != ~0xffff) && ((val & ~0xffff) != 0))
- return bfd_reloc_overflow;
+ location = (bfd_byte *) data + reloc_entry->address;
+ _bfd_mips16_elf_reloc_unshuffle (abfd, reloc_entry->howto->type, FALSE,
+ location);
+ ret = _bfd_mips_elf_gprel16_with_gp (abfd, symbol, reloc_entry,
+ input_section, relocatable,
+ data, gp);
+ _bfd_mips16_elf_reloc_shuffle (abfd, reloc_entry->howto->type, !relocatable,
+ location);
- return bfd_reloc_ok;
+ return ret;
}
/* A mapping from BFD reloc types to MIPS ELF reloc types. */
@@ -1637,6 +1704,14 @@ static const struct elf_reloc_map mips_r
{ BFD_RELOC_MIPS_JALR, R_MIPS_JALR }
};
+static const struct elf_reloc_map mips16_reloc_map[] =
+{
+ { BFD_RELOC_MIPS16_JMP, R_MIPS16_26 - R_MIPS16_min },
+ { BFD_RELOC_MIPS16_GPREL, R_MIPS16_GPREL - R_MIPS16_min },
+ { BFD_RELOC_MIPS16_HI16_S, R_MIPS16_HI16 - R_MIPS16_min },
+ { BFD_RELOC_MIPS16_LO16, R_MIPS16_LO16 - R_MIPS16_min },
+};
+
/* Given a BFD reloc type, return a howto structure. */
static reloc_howto_type *
@@ -1647,6 +1722,7 @@ bfd_elf32_bfd_reloc_type_lookup (bfd *ab
/* FIXME: We default to RELA here instead of choosing the right
relocation variant. */
reloc_howto_type *howto_table = elf_mips_howto_table_rela;
+ reloc_howto_type *howto16_table = elf_mips16_howto_table_rela;
for (i = 0; i < sizeof (mips_reloc_map) / sizeof (struct elf_reloc_map);
i++)
@@ -1655,12 +1731,15 @@ bfd_elf32_bfd_reloc_type_lookup (bfd *ab
return &howto_table[(int) mips_reloc_map[i].elf_val];
}
+ for (i = 0; i < sizeof (mips16_reloc_map) / sizeof (struct elf_reloc_map);
+ i++)
+ {
+ if (mips16_reloc_map[i].bfd_val == code)
+ return &howto16_table[(int) mips16_reloc_map[i].elf_val];
+ }
+
switch (code)
{
- case BFD_RELOC_MIPS16_JMP:
- return &elf_mips16_jump_howto;
- case BFD_RELOC_MIPS16_GPREL:
- return &elf_mips16_gprel_howto;
case BFD_RELOC_VTABLE_INHERIT:
return &elf_mips_gnu_vtinherit_howto;
case BFD_RELOC_VTABLE_ENTRY:
@@ -1680,10 +1759,6 @@ mips_elf_n32_rtype_to_howto (unsigned in
{
switch (r_type)
{
- case R_MIPS16_26:
- return &elf_mips16_jump_howto;
- case R_MIPS16_GPREL:
- return &elf_mips16_gprel_howto;
case R_MIPS_GNU_VTINHERIT:
return &elf_mips_gnu_vtinherit_howto;
case R_MIPS_GNU_VTENTRY:
@@ -1694,6 +1769,13 @@ mips_elf_n32_rtype_to_howto (unsigned in
else
return &elf_mips_gnu_rel16_s2;
default:
+ if (r_type >= R_MIPS16_min && r_type < R_MIPS16_max)
+ {
+ if (rela_p)
+ return &elf_mips16_howto_table_rela[r_type - R_MIPS16_min];
+ else
+ return &elf_mips16_howto_table_rel[r_type - R_MIPS16_min];
+ }
BFD_ASSERT (r_type < (unsigned int) R_MIPS_max);
if (rela_p)
return &elf_mips_howto_table_rela[r_type];
diff -up --recursive --new-file binutils-2.15.94-20050214.macro/bfd/elfxx-mips.c binutils-2.15.94-20050214/bfd/elfxx-mips.c
--- binutils-2.15.94-20050214.macro/bfd/elfxx-mips.c 2005-02-01 01:11:15.000000000 +0000
+++ binutils-2.15.94-20050214/bfd/elfxx-mips.c 2005-02-15 17:04:34.000000000 +0000
@@ -1061,6 +1061,152 @@ mips_elf_check_mips16_stubs (struct mips
return TRUE;
}
+/* R_MIPS16_26 is used for the mips16 jal and jalx instructions.
+ Most mips16 instructions are 16 bits, but these instructions
+ are 32 bits.
+
+ The format of these instructions is:
+
+ +--------------+--------------------------------+
+ | JALX | X| Imm 20:16 | Imm 25:21 |
+ +--------------+--------------------------------+
+ | Immediate 15:0 |
+ +-----------------------------------------------+
+
+ JALX is the 5-bit value 00011. X is 0 for jal, 1 for jalx.
+ Note that the immediate value in the first word is swapped.
+
+ When producing a relocatable object file, R_MIPS16_26 is
+ handled mostly like R_MIPS_26. In particular, the addend is
+ stored as a straight 26-bit value in a 32-bit instruction.
+ (gas makes life simpler for itself by never adjusting a
+ R_MIPS16_26 reloc to be against a section, so the addend is
+ always zero). However, the 32 bit instruction is stored as 2
+ 16-bit values, rather than a single 32-bit value. In a
+ big-endian file, the result is the same; in a little-endian
+ file, the two 16-bit halves of the 32 bit value are swapped.
+ This is so that a disassembler can recognize the jal
+ instruction.
+
+ When doing a final link, R_MIPS16_26 is treated as a 32 bit
+ instruction stored as two 16-bit values. The addend A is the
+ contents of the targ26 field. The calculation is the same as
+ R_MIPS_26. When storing the calculated value, reorder the
+ immediate value as shown above, and don't forget to store the
+ value as two 16-bit values.
+
+ To put it in MIPS ABI terms, the relocation field is T-targ26-16,
+ defined as
+
+ big-endian:
+ +--------+----------------------+
+ | | |
+ | | targ26-16 |
+ |31 26|25 0|
+ +--------+----------------------+
+
+ little-endian:
+ +----------+------+-------------+
+ | | | |
+ | sub1 | | sub2 |
+ |0 9|10 15|16 31|
+ +----------+--------------------+
+ where targ26-16 is sub1 followed by sub2 (i.e., the addend field A is
+ ((sub1 << 16) | sub2)).
+
+ When producing a relocatable object file, the calculation is
+ (((A < 2) | ((P + 4) & 0xf0000000) + S) >> 2)
+ When producing a fully linked file, the calculation is
+ let R = (((A < 2) | ((P + 4) & 0xf0000000) + S) >> 2)
+ ((R & 0x1f0000) << 5) | ((R & 0x3e00000) >> 5) | (R & 0xffff)
+
+ R_MIPS16_GPREL is used for GP-relative addressing in mips16
+ mode. A typical instruction will have a format like this:
+
+ +--------------+--------------------------------+
+ | EXTEND | Imm 10:5 | Imm 15:11 |
+ +--------------+--------------------------------+
+ | Major | rx | ry | Imm 4:0 |
+ +--------------+--------------------------------+
+
+ EXTEND is the five bit value 11110. Major is the instruction
+ opcode.
+
+ This is handled exactly like R_MIPS_GPREL16, except that the
+ addend is retrieved and stored as shown in this diagram; that
+ is, the Imm fields above replace the V-rel16 field.
+
+ All we need to do here is shuffle the bits appropriately. As
+ above, the two 16-bit halves must be swapped on a
+ little-endian system.
+
+ R_MIPS16_HI16 and R_MIPS16_LO16 are used in mips16 mode to
+ access data when neither GP-relative nor PC-relative addressing
+ can be used. They are handled like R_MIPS_HI16 and R_MIPS_LO16,
+ except that the addend is retrieved and stored as shown above
+ for R_MIPS16_GPREL.
+ */
+void
+_bfd_mips16_elf_reloc_unshuffle (bfd *abfd, int r_type,
+ bfd_boolean jal_shuffle, bfd_byte *data)
+{
+ bfd_vma extend, insn, val;
+
+ if (r_type != R_MIPS16_26 && r_type != R_MIPS16_GPREL
+ && r_type != R_MIPS16_HI16 && r_type != R_MIPS16_LO16)
+ return;
+
+ /* Pick up the mips16 extend instruction and the real instruction. */
+ extend = bfd_get_16 (abfd, data);
+ insn = bfd_get_16 (abfd, data + 2);
+ if (r_type == R_MIPS16_26)
+ {
+ if (jal_shuffle)
+ val = ((extend & 0xfc00) << 16) | ((extend & 0x3e0) << 11)
+ | ((extend & 0x1f) << 21) | insn;
+ else
+ val = extend << 16 | insn;
+ }
+ else
+ val = ((extend & 0xf800) << 16) | ((insn & 0xffe0) << 11)
+ | ((extend & 0x1f) << 11) | (extend & 0x7e0) | (insn & 0x1f);
+ bfd_put_32 (abfd, val, data);
+}
+
+void
+_bfd_mips16_elf_reloc_shuffle (bfd *abfd, int r_type,
+ bfd_boolean jal_shuffle, bfd_byte *data)
+{
+ bfd_vma extend, insn, val;
+
+ if (r_type != R_MIPS16_26 && r_type != R_MIPS16_GPREL
+ && r_type != R_MIPS16_HI16 && r_type != R_MIPS16_LO16)
+ return;
+
+ val = bfd_get_32 (abfd, data);
+ if (r_type == R_MIPS16_26)
+ {
+ if (jal_shuffle)
+ {
+ insn = val & 0xffff;
+ extend = ((val >> 16) & 0xfc00) | ((val >> 11) & 0x3e0)
+ | ((val >> 21) & 0x1f);
+ }
+ else
+ {
+ insn = val & 0xffff;
+ extend = val >> 16;
+ }
+ }
+ else
+ {
+ insn = ((val >> 11) & 0xffe0) | (val & 0x1f);
+ extend = ((val >> 16) & 0xf800) | ((val >> 11) & 0x1f) | (val & 0x7e0);
+ }
+ bfd_put_16 (abfd, insn, data + 2);
+ bfd_put_16 (abfd, extend, data);
+}
+
bfd_reloc_status_type
_bfd_mips_elf_gprel16_with_gp (bfd *abfd, asymbol *symbol,
arelent *reloc_entry, asection *input_section,
@@ -1194,11 +1340,17 @@ _bfd_mips_elf_lo16_reloc (bfd *abfd, are
bfd *output_bfd, char **error_message)
{
bfd_vma vallo;
+ bfd_byte *location = (bfd_byte *) data + reloc_entry->address;
if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
return bfd_reloc_outofrange;
- vallo = bfd_get_32 (abfd, (bfd_byte *) data + reloc_entry->address);
+ _bfd_mips16_elf_reloc_unshuffle (abfd, reloc_entry->howto->type, FALSE,
+ location);
+ vallo = bfd_get_32 (abfd, location);
+ _bfd_mips16_elf_reloc_shuffle (abfd, reloc_entry->howto->type, FALSE,
+ location);
+
while (mips_hi16_list != NULL)
{
bfd_reloc_status_type ret;
@@ -1284,13 +1436,19 @@ _bfd_mips_elf_generic_reloc (bfd *abfd A
reloc_entry->addend += val;
else
{
+ bfd_byte *location = (bfd_byte *) data + reloc_entry->address;
+
/* Add in the separate addend, if any. */
val += reloc_entry->addend;
/* Add VAL to the relocation field. */
+ _bfd_mips16_elf_reloc_unshuffle (abfd, reloc_entry->howto->type, FALSE,
+ location);
status = _bfd_relocate_contents (reloc_entry->howto, abfd, val,
- (bfd_byte *) data
- + reloc_entry->address);
+ location);
+ _bfd_mips16_elf_reloc_shuffle (abfd, reloc_entry->howto->type, FALSE,
+ location);
+
if (status != bfd_reloc_ok)
return status;
}
@@ -3078,7 +3236,8 @@ mips_elf_calculate_relocation (bfd *abfd
{
/* Relocations against _gp_disp are permitted only with
R_MIPS_HI16 and R_MIPS_LO16 relocations. */
- if (r_type != R_MIPS_HI16 && r_type != R_MIPS_LO16)
+ if (r_type != R_MIPS_HI16 && r_type != R_MIPS_LO16
+ && r_type != R_MIPS16_HI16 && r_type != R_MIPS16_LO16)
return bfd_reloc_notsupported;
gp_disp_p = TRUE;
@@ -3265,10 +3424,12 @@ mips_elf_calculate_relocation (bfd *abfd
case R_MIPS_HI16:
case R_MIPS_LO16:
- case R_MIPS16_GPREL:
case R_MIPS_GPREL16:
case R_MIPS_GPREL32:
case R_MIPS_LITERAL:
+ case R_MIPS16_HI16:
+ case R_MIPS16_LO16:
+ case R_MIPS16_GPREL:
gp0 = _bfd_get_gp_value (input_bfd);
gp = _bfd_get_gp_value (abfd);
if (elf_hash_table (info)->dynobj)
@@ -3360,6 +3521,7 @@ mips_elf_calculate_relocation (bfd *abfd
break;
case R_MIPS_HI16:
+ case R_MIPS16_HI16:
if (!gp_disp_p)
{
value = mips_elf_high (addend + symbol);
@@ -3367,17 +3529,35 @@ mips_elf_calculate_relocation (bfd *abfd
}
else
{
- value = mips_elf_high (addend + gp - p);
+ /* For MIPS16 ABI code we generate this sequence
+ 0: li $v0,%hi(_gp_disp)
+ 4: addiupc $v1,%lo(_gp_disp)
+ 8: sll $v0,16
+ 12: addu $v0,$v1
+ 14: move $gp,$v0
+ So the offsets of hi and lo relocs are the same, but the
+ $pc is four higher than $t9 would be, so reduce
+ both reloc addends by 4. */
+ if (r_type == R_MIPS16_HI16)
+ value = mips_elf_high (addend + gp - p - 4);
+ else
+ value = mips_elf_high (addend + gp - p);
overflowed_p = mips_elf_overflow_p (value, 16);
}
break;
case R_MIPS_LO16:
+ case R_MIPS16_LO16:
if (!gp_disp_p)
value = (symbol + addend) & howto->dst_mask;
else
{
- value = addend + gp - p + 4;
+ /* See the comment for R_MIPS16_HI16 above for the reason
+ for this conditional. */
+ if (r_type == R_MIPS16_LO16)
+ value = addend + gp - p;
+ else
+ value = addend + gp - p + 4;
/* The MIPS ABI requires checking the R_MIPS_LO16 relocation
for overflow. But, on, say, IRIX5, relocations against
_gp_disp are normally generated from the .cpload
@@ -3563,13 +3743,6 @@ mips_elf_obtain_contents (reloc_howto_ty
/* Obtain the bytes. */
x = bfd_get ((8 * bfd_get_reloc_size (howto)), input_bfd, location);
- if ((ELF_R_TYPE (input_bfd, relocation->r_info) == R_MIPS16_26
- || ELF_R_TYPE (input_bfd, relocation->r_info) == R_MIPS16_GPREL)
- && bfd_little_endian (input_bfd))
- /* The two 16-bit words will be reversed on a little-endian system.
- See mips_elf_perform_relocation for more details. */
- x = (((x & 0xffff) << 16) | ((x & 0xffff0000) >> 16));
-
return x;
}
@@ -3597,107 +3770,14 @@ mips_elf_perform_relocation (struct bfd_
/* Figure out where the relocation is occurring. */
location = contents + relocation->r_offset;
+ _bfd_mips16_elf_reloc_unshuffle (input_bfd, r_type, FALSE, location);
+
/* Obtain the current value. */
x = mips_elf_obtain_contents (howto, relocation, input_bfd, contents);
/* Clear the field we are setting. */
x &= ~howto->dst_mask;
- /* If this is the R_MIPS16_26 relocation, we must store the
- value in a funny way. */
- if (r_type == R_MIPS16_26)
- {
- /* R_MIPS16_26 is used for the mips16 jal and jalx instructions.
- Most mips16 instructions are 16 bits, but these instructions
- are 32 bits.
-
- The format of these instructions is:
-
- +--------------+--------------------------------+
- ! JALX ! X! Imm 20:16 ! Imm 25:21 !
- +--------------+--------------------------------+
- ! Immediate 15:0 !
- +-----------------------------------------------+
-
- JALX is the 5-bit value 00011. X is 0 for jal, 1 for jalx.
- Note that the immediate value in the first word is swapped.
-
- When producing a relocatable object file, R_MIPS16_26 is
- handled mostly like R_MIPS_26. In particular, the addend is
- stored as a straight 26-bit value in a 32-bit instruction.
- (gas makes life simpler for itself by never adjusting a
- R_MIPS16_26 reloc to be against a section, so the addend is
- always zero). However, the 32 bit instruction is stored as 2
- 16-bit values, rather than a single 32-bit value. In a
- big-endian file, the result is the same; in a little-endian
- file, the two 16-bit halves of the 32 bit value are swapped.
- This is so that a disassembler can recognize the jal
- instruction.
-
- When doing a final link, R_MIPS16_26 is treated as a 32 bit
- instruction stored as two 16-bit values. The addend A is the
- contents of the targ26 field. The calculation is the same as
- R_MIPS_26. When storing the calculated value, reorder the
- immediate value as shown above, and don't forget to store the
- value as two 16-bit values.
-
- To put it in MIPS ABI terms, the relocation field is T-targ26-16,
- defined as
-
- big-endian:
- +--------+----------------------+
- | | |
- | | targ26-16 |
- |31 26|25 0|
- +--------+----------------------+
-
- little-endian:
- +----------+------+-------------+
- | | | |
- | sub1 | | sub2 |
- |0 9|10 15|16 31|
- +----------+--------------------+
- where targ26-16 is sub1 followed by sub2 (i.e., the addend field A is
- ((sub1 << 16) | sub2)).
-
- When producing a relocatable object file, the calculation is
- (((A < 2) | ((P + 4) & 0xf0000000) + S) >> 2)
- When producing a fully linked file, the calculation is
- let R = (((A < 2) | ((P + 4) & 0xf0000000) + S) >> 2)
- ((R & 0x1f0000) << 5) | ((R & 0x3e00000) >> 5) | (R & 0xffff) */
-
- if (!info->relocatable)
- /* Shuffle the bits according to the formula above. */
- value = (((value & 0x1f0000) << 5)
- | ((value & 0x3e00000) >> 5)
- | (value & 0xffff));
- }
- else if (r_type == R_MIPS16_GPREL)
- {
- /* R_MIPS16_GPREL is used for GP-relative addressing in mips16
- mode. A typical instruction will have a format like this:
-
- +--------------+--------------------------------+
- ! EXTEND ! Imm 10:5 ! Imm 15:11 !
- +--------------+--------------------------------+
- ! Major ! rx ! ry ! Imm 4:0 !
- +--------------+--------------------------------+
-
- EXTEND is the five bit value 11110. Major is the instruction
- opcode.
-
- This is handled exactly like R_MIPS_GPREL16, except that the
- addend is retrieved and stored as shown in this diagram; that
- is, the Imm fields above replace the V-rel16 field.
-
- All we need to do here is shuffle the bits appropriately. As
- above, the two 16-bit halves must be swapped on a
- little-endian system. */
- value = (((value & 0x7e0) << 16)
- | ((value & 0xf800) << 5)
- | (value & 0x1f));
- }
-
/* Set the field. */
x |= (value & howto->dst_mask);
@@ -3763,14 +3843,12 @@ mips_elf_perform_relocation (struct bfd_
x = 0x04110000 | (((bfd_vma) off >> 2) & 0xffff); /* bal addr */
}
- /* Swap the high- and low-order 16 bits on little-endian systems
- when doing a MIPS16 relocation. */
- if ((r_type == R_MIPS16_GPREL || r_type == R_MIPS16_26)
- && bfd_little_endian (input_bfd))
- x = (((x & 0xffff) << 16) | ((x & 0xffff0000) >> 16));
-
/* Put the value into the output. */
bfd_put (8 * bfd_get_reloc_size (howto), input_bfd, x, location);
+
+ _bfd_mips16_elf_reloc_shuffle(input_bfd, r_type, !info->relocatable,
+ location);
+
return TRUE;
}
@@ -6290,18 +6368,25 @@ _bfd_mips_elf_relocate_section (bfd *out
rel_hdr = elf_section_data (input_section)->rel_hdr2;
if (rel_hdr->sh_entsize == MIPS_ELF_REL_SIZE (input_bfd))
{
+ bfd_byte *location = contents + rel->r_offset;
+
/* Note that this is a REL relocation. */
rela_relocation_p = FALSE;
/* Get the addend, which is stored in the input file. */
+ _bfd_mips16_elf_reloc_unshuffle (input_bfd, r_type, FALSE,
+ location);
addend = mips_elf_obtain_contents (howto, rel, input_bfd,
contents);
+ _bfd_mips16_elf_reloc_shuffle(input_bfd, r_type, FALSE,
+ location);
+
addend &= howto->src_mask;
/* For some kinds of relocations, the ADDEND is a
combination of the addend stored in two different
relocations. */
- if (r_type == R_MIPS_HI16
+ if (r_type == R_MIPS_HI16 || r_type == R_MIPS16_HI16
|| (r_type == R_MIPS_GOT16
&& mips_elf_local_relocation_p (input_bfd, rel,
local_sections, FALSE)))
@@ -6309,6 +6394,13 @@ _bfd_mips_elf_relocate_section (bfd *out
bfd_vma l;
const Elf_Internal_Rela *lo16_relocation;
reloc_howto_type *lo16_howto;
+ bfd_byte *lo16_location;
+ int lo16_type;
+
+ if (r_type == R_MIPS16_HI16)
+ lo16_type = R_MIPS16_LO16;
+ else
+ lo16_type = R_MIPS_LO16;
/* The combined value is the sum of the HI16 addend,
left-shifted by sixteen bits, and the LO16
@@ -6327,16 +6419,22 @@ _bfd_mips_elf_relocate_section (bfd *out
as one of these. We permit a similar extension
in general, as that is useful for GCC. */
lo16_relocation = mips_elf_next_relocation (input_bfd,
- R_MIPS_LO16,
+ lo16_type,
rel, relend);
if (lo16_relocation == NULL)
return FALSE;
+ lo16_location = contents + lo16_relocation->r_offset;
+
/* Obtain the addend kept there. */
lo16_howto = MIPS_ELF_RTYPE_TO_HOWTO (input_bfd,
- R_MIPS_LO16, FALSE);
+ lo16_type, FALSE);
+ _bfd_mips16_elf_reloc_unshuffle (input_bfd, lo16_type, FALSE,
+ lo16_location);
l = mips_elf_obtain_contents (lo16_howto, lo16_relocation,
input_bfd, contents);
+ _bfd_mips16_elf_reloc_shuffle (input_bfd, lo16_type, FALSE,
+ lo16_location);
l &= lo16_howto->src_mask;
l <<= lo16_howto->rightshift;
l = _bfd_mips_elf_sign_extend (l, 16);
@@ -6346,15 +6444,6 @@ _bfd_mips_elf_relocate_section (bfd *out
/* Compute the combined addend. */
addend += l;
}
- else if (r_type == R_MIPS16_GPREL)
- {
- /* The addend is scrambled in the object file. See
- mips_elf_perform_relocation for details on the
- format. */
- addend = (((addend & 0x1f0000) >> 5)
- | ((addend & 0x7e00000) >> 16)
- | (addend & 0x1f));
- }
else
addend <<= howto->rightshift;
}
diff -up --recursive --new-file binutils-2.15.94-20050214.macro/bfd/elfxx-mips.h binutils-2.15.94-20050214/bfd/elfxx-mips.h
--- binutils-2.15.94-20050214.macro/bfd/elfxx-mips.h 2005-01-31 20:39:10.000000000 +0000
+++ binutils-2.15.94-20050214/bfd/elfxx-mips.h 2005-02-11 23:03:22.000000000 +0000
@@ -103,6 +103,10 @@ extern bfd_boolean _bfd_mips_elf_write_s
extern bfd_boolean _bfd_mips_elf_read_ecoff_info
(bfd *, asection *, struct ecoff_debug_info *);
+extern void _bfd_mips16_elf_reloc_unshuffle
+ (bfd *, int, bfd_boolean, bfd_byte *);
+extern void _bfd_mips16_elf_reloc_shuffle
+ (bfd *, int, bfd_boolean, bfd_byte *);
extern bfd_reloc_status_type _bfd_mips_elf_gprel16_with_gp
(bfd *, asymbol *, arelent *, asection *, bfd_boolean, void *, bfd_vma);
extern bfd_reloc_status_type _bfd_mips_elf32_gprel16_reloc
diff -up --recursive --new-file binutils-2.15.94-20050214.macro/bfd/libbfd.h binutils-2.15.94-20050214/bfd/libbfd.h
--- binutils-2.15.94-20050214.macro/bfd/libbfd.h 2005-01-25 20:22:23.000000000 +0000
+++ binutils-2.15.94-20050214/bfd/libbfd.h 2005-02-11 23:03:22.000000000 +0000
@@ -902,6 +902,9 @@ static const char *const bfd_reloc_code_
"BFD_RELOC_HI16",
"BFD_RELOC_HI16_S",
"BFD_RELOC_LO16",
+ "BFD_RELOC_MIPS16_HI16",
+ "BFD_RELOC_MIPS16_HI16_S",
+ "BFD_RELOC_MIPS16_LO16",
"BFD_RELOC_MIPS_LITERAL",
"BFD_RELOC_MIPS_GOT16",
"BFD_RELOC_MIPS_CALL16",
diff -up --recursive --new-file binutils-2.15.94-20050214.macro/bfd/reloc.c binutils-2.15.94-20050214/bfd/reloc.c
--- binutils-2.15.94-20050214.macro/bfd/reloc.c 2005-01-31 23:13:29.000000000 +0000
+++ binutils-2.15.94-20050214/bfd/reloc.c 2005-02-11 23:03:22.000000000 +0000
@@ -2063,6 +2063,22 @@ ENUMDOC
Low 16 bits.
ENUM
+ BFD_RELOC_MIPS16_HI16
+ENUMDOC
+ MIPS16 high 16 bits of 32-bit value.
+ENUM
+ BFD_RELOC_MIPS16_HI16_S
+ENUMDOC
+ MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
+ extended and added to form the final result. If the low 16
+ bits form a negative number, we need to add one to the high value
+ to compensate for the borrow when the low bits are added.
+ENUM
+ BFD_RELOC_MIPS16_LO16
+ENUMDOC
+ MIPS16 low 16 bits.
+
+ENUM
BFD_RELOC_MIPS_LITERAL
ENUMDOC
Relocation against a MIPS literal section.
diff -up --recursive --new-file binutils-2.15.94-20050214.macro/gas/config/tc-mips.c binutils-2.15.94-20050214/gas/config/tc-mips.c
--- binutils-2.15.94-20050214.macro/gas/config/tc-mips.c 2005-01-31 23:18:30.000000000 +0000
+++ binutils-2.15.94-20050214/gas/config/tc-mips.c 2005-02-11 23:03:22.000000000 +0000
@@ -1407,7 +1407,8 @@ reloc_needs_lo_p (bfd_reloc_code_real_ty
{
return (HAVE_IN_PLACE_ADDENDS
&& (reloc == BFD_RELOC_HI16_S
- || reloc == BFD_RELOC_MIPS_GOT16));
+ || reloc == BFD_RELOC_MIPS_GOT16
+ || reloc == BFD_RELOC_MIPS16_HI16_S));
}
/* Return true if the given fixup is followed by a matching R_MIPS_LO16
@@ -1417,7 +1418,8 @@ static inline bfd_boolean
fixup_has_matching_lo_p (fixS *fixp)
{
return (fixp->fx_next != NULL
- && fixp->fx_next->fx_r_type == BFD_RELOC_LO16
+ && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16
+ || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16)
&& fixp->fx_addsy == fixp->fx_next->fx_addsy
&& fixp->fx_offset == fixp->fx_next->fx_offset);
}
@@ -2194,7 +2196,10 @@ append_insn (struct mips_cl_insn *ip, ex
|| reloc_type[0] == BFD_RELOC_MIPS_HIGHER
|| reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
|| reloc_type[0] == BFD_RELOC_MIPS_REL16
- || reloc_type[0] == BFD_RELOC_MIPS_RELGOT))
+ || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
+ || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
+ || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S
+ || reloc_type[0] == BFD_RELOC_MIPS16_LO16))
fixp[0]->fx_no_overflow = 1;
if (mips_relax.sequence)
@@ -9097,6 +9102,7 @@ mips16_ip (char *str, struct mips_cl_ins
unsigned int regno;
unsigned int lastregno = 0;
char *s_reset;
+ size_t i;
insn_error = NULL;
@@ -9183,8 +9189,34 @@ mips16_ip (char *str, struct mips_cl_ins
&& *imm_reloc > BFD_RELOC_UNUSED
&& insn->pinfo != INSN_MACRO)
{
+ valueT tmp;
+
+ switch (*offset_reloc)
+ {
+ case BFD_RELOC_MIPS16_HI16_S:
+ tmp = (imm_expr.X_add_number + 0x8000) >> 16;
+ break;
+
+ case BFD_RELOC_MIPS16_HI16:
+ tmp = imm_expr.X_add_number >> 16;
+ break;
+
+ case BFD_RELOC_MIPS16_LO16:
+ tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
+ - 0x8000;
+ break;
+
+ case BFD_RELOC_UNUSED:
+ tmp = imm_expr.X_add_number;
+ break;
+
+ default:
+ internalError ();
+ }
+ *offset_reloc = BFD_RELOC_UNUSED;
+
mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
- imm_expr.X_add_number, TRUE, mips16_small,
+ tmp, TRUE, mips16_small,
mips16_ext, &ip->insn_opcode,
&ip->use_extend, &ip->extend);
imm_expr.X_op = O_absent;
@@ -9395,47 +9427,43 @@ mips16_ip (char *str, struct mips_cl_ins
}
break;
- case '<':
- case '>':
- case '[':
- case ']':
- case '4':
case '5':
case 'H':
case 'W':
case 'D':
case 'j':
- case '8':
case 'V':
case 'C':
case 'U':
case 'k':
case 'K':
- if (s[0] == '%'
- && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
+ i = my_getSmallExpression (&imm_expr, imm_reloc, s);
+ if (i > 0)
{
- /* This is %gprel(SYMBOL). We need to read SYMBOL,
- and generate the appropriate reloc. If the text
- inside %gprel is not a symbol name with an
- optional offset, then we generate a normal reloc
- and will probably fail later. */
- my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
- if (imm_expr.X_op == O_symbol)
+ if (imm_expr.X_op != O_constant)
{
mips16_ext = TRUE;
- *imm_reloc = BFD_RELOC_MIPS16_GPREL;
- s = expr_end;
ip->use_extend = TRUE;
ip->extend = 0;
- continue;
}
+ else
+ {
+ /* We need to relax this instruction. */
+ *offset_reloc = *imm_reloc;
+ *imm_reloc = (int) BFD_RELOC_UNUSED + c;
+ }
+ s = expr_end;
+ continue;
}
- else
- {
- /* Just pick up a normal expression. */
- my_getExpression (&imm_expr, s);
- }
-
+ *imm_reloc = BFD_RELOC_UNUSED;
+ /* Fall through. */
+ case '<':
+ case '>':
+ case '[':
+ case ']':
+ case '4':
+ case '8':
+ my_getExpression (&imm_expr, s);
if (imm_expr.X_op == O_register)
{
/* What we thought was an expression turned out to
@@ -9797,11 +9825,13 @@ mips16_immed (char *file, unsigned int l
}
}
-static const struct percent_op_match
+struct percent_op_match
{
const char *str;
bfd_reloc_code_real_type reloc;
-} percent_op[] =
+};
+
+static const struct percent_op_match mips_percent_op[] =
{
{"%lo", BFD_RELOC_LO16},
#ifdef OBJ_ELF
@@ -9823,6 +9853,13 @@ static const struct percent_op_match
{"%hi", BFD_RELOC_HI16_S}
};
+static const struct percent_op_match mips16_percent_op[] =
+{
+ {"%lo", BFD_RELOC_MIPS16_LO16},
+ {"%gprel", BFD_RELOC_MIPS16_GPREL},
+ {"%hi", BFD_RELOC_MIPS16_HI16_S}
+};
+
/* Return true if *STR points to a relocation operator. When returning true,
move *STR over the operator and store its relocation code in *RELOC.
@@ -9831,9 +9868,21 @@ static const struct percent_op_match
static bfd_boolean
parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
{
- size_t i;
+ const struct percent_op_match *percent_op;
+ size_t limit, i;
+
+ if (mips_opts.mips16)
+ {
+ percent_op = mips16_percent_op;
+ limit = ARRAY_SIZE (mips16_percent_op);
+ }
+ else
+ {
+ percent_op = mips_percent_op;
+ limit = ARRAY_SIZE (mips_percent_op);
+ }
- for (i = 0; i < ARRAY_SIZE (percent_op); i++)
+ for (i = 0; i < limit; i++)
if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
{
*str += strlen (percent_op[i].str);
@@ -11000,6 +11049,8 @@ md_apply_fix3 (fixS *fixP, valueT *valP,
case BFD_RELOC_MIPS_CALL_HI16:
case BFD_RELOC_MIPS_CALL_LO16:
case BFD_RELOC_MIPS16_GPREL:
+ case BFD_RELOC_MIPS16_HI16:
+ case BFD_RELOC_MIPS16_HI16_S:
assert (! fixP->fx_pcrel);
/* Nothing needed to do. The value comes from the reloc entry */
break;
@@ -11051,6 +11102,7 @@ md_apply_fix3 (fixS *fixP, valueT *valP,
break;
case BFD_RELOC_LO16:
+ case BFD_RELOC_MIPS16_LO16:
/* FIXME: Now that embedded-PIC is gone, some of this code/comment
may be safe to remove, but if so it's not obvious. */
/* When handling an embedded PIC switch statement, we can wind
diff -up --recursive --new-file binutils-2.15.94-20050214.macro/gas/testsuite/gas/mips/mips.exp binutils-2.15.94-20050214/gas/testsuite/gas/mips/mips.exp
--- binutils-2.15.94-20050214.macro/gas/testsuite/gas/mips/mips.exp 2004-12-10 19:48:42.000000000 +0000
+++ binutils-2.15.94-20050214/gas/testsuite/gas/mips/mips.exp 2005-02-11 23:08:22.000000000 +0000
@@ -529,6 +529,11 @@ if { [istarget mips*-*-*] } then {
# Check jalx handling
run_dump_test "mips16-jalx"
run_dump_test "mips-jalx"
+ # Check MIPS16 HI16/LO16 relocations
+ run_dump_test "mips16-hilo"
+ if $has_newabi {
+ run_dump_test "mips16-hilo-n32"
+ }
}
run_list_test "mips-no-jalx" "-32"
run_dump_test "delay"
diff -up --recursive --new-file binutils-2.15.94-20050214.macro/gas/testsuite/gas/mips/mips16-hilo-n32.d binutils-2.15.94-20050214/gas/testsuite/gas/mips/mips16-hilo-n32.d
--- binutils-2.15.94-20050214.macro/gas/testsuite/gas/mips/mips16-hilo-n32.d 1970-01-01 00:00:00.000000000 +0000
+++ binutils-2.15.94-20050214/gas/testsuite/gas/mips/mips16-hilo-n32.d 2005-02-11 13:08:49.000000000 +0000
@@ -0,0 +1,527 @@
+#objdump: -dr
+#name: MIPS16 lui/addi n32
+#as: -mips16 -mabi=n32 -march=mips64
+#source: mips16-hilo.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+0+0000 <stuff>:
+ 0: 6c00 li a0,0
+ 2: f400 3480 sll a0,16
+ 6: 4c00 addiu a0,0
+ 8: f000 6c00 li a0,0
+ 8: R_MIPS16_HI16 \.data
+ c: f400 3480 sll a0,16
+ 10: f000 4c00 addiu a0,0
+ 10: R_MIPS16_LO16 \.data
+ 14: f000 6c00 li a0,0
+ 14: R_MIPS16_HI16 \.data\+0x4
+ 18: f400 3480 sll a0,16
+ 1c: f000 4c00 addiu a0,0
+ 1c: R_MIPS16_LO16 \.data\+0x4
+ 20: f000 6c00 li a0,0
+ 20: R_MIPS16_HI16 big_external_data_label
+ 24: f400 3480 sll a0,16
+ 28: f000 4c00 addiu a0,0
+ 28: R_MIPS16_LO16 big_external_data_label
+ 2c: f000 6c00 li a0,0
+ 2c: R_MIPS16_HI16 small_external_data_label
+ 30: f400 3480 sll a0,16
+ 34: f000 4c00 addiu a0,0
+ 34: R_MIPS16_LO16 small_external_data_label
+ 38: f000 6c00 li a0,0
+ 38: R_MIPS16_HI16 big_external_common
+ 3c: f400 3480 sll a0,16
+ 40: f000 4c00 addiu a0,0
+ 40: R_MIPS16_LO16 big_external_common
+ 44: f000 6c00 li a0,0
+ 44: R_MIPS16_HI16 small_external_common
+ 48: f400 3480 sll a0,16
+ 4c: f000 4c00 addiu a0,0
+ 4c: R_MIPS16_LO16 small_external_common
+ 50: f000 6c00 li a0,0
+ 50: R_MIPS16_HI16 \.bss
+ 54: f400 3480 sll a0,16
+ 58: f000 4c00 addiu a0,0
+ 58: R_MIPS16_LO16 \.bss
+ 5c: f000 6c00 li a0,0
+ 5c: R_MIPS16_HI16 \.sbss
+ 60: f400 3480 sll a0,16
+ 64: f000 4c00 addiu a0,0
+ 64: R_MIPS16_LO16 \.sbss
+ 68: 6c00 li a0,0
+ 6a: f400 3480 sll a0,16
+ 6e: 4c01 addiu a0,1
+ 70: f000 6c00 li a0,0
+ 70: R_MIPS16_HI16 \.data\+0x1
+ 74: f400 3480 sll a0,16
+ 78: f000 4c00 addiu a0,0
+ 78: R_MIPS16_LO16 \.data\+0x1
+ 7c: f000 6c00 li a0,0
+ 7c: R_MIPS16_HI16 \.data\+0x5
+ 80: f400 3480 sll a0,16
+ 84: f000 4c00 addiu a0,0
+ 84: R_MIPS16_LO16 \.data\+0x5
+ 88: f000 6c00 li a0,0
+ 88: R_MIPS16_HI16 big_external_data_label\+0x1
+ 8c: f400 3480 sll a0,16
+ 90: f000 4c00 addiu a0,0
+ 90: R_MIPS16_LO16 big_external_data_label\+0x1
+ 94: f000 6c00 li a0,0
+ 94: R_MIPS16_HI16 small_external_data_label\+0x1
+ 98: f400 3480 sll a0,16
+ 9c: f000 4c00 addiu a0,0
+ 9c: R_MIPS16_LO16 small_external_data_label\+0x1
+ a0: f000 6c00 li a0,0
+ a0: R_MIPS16_HI16 big_external_common\+0x1
+ a4: f400 3480 sll a0,16
+ a8: f000 4c00 addiu a0,0
+ a8: R_MIPS16_LO16 big_external_common\+0x1
+ ac: f000 6c00 li a0,0
+ ac: R_MIPS16_HI16 small_external_common\+0x1
+ b0: f400 3480 sll a0,16
+ b4: f000 4c00 addiu a0,0
+ b4: R_MIPS16_LO16 small_external_common\+0x1
+ b8: f000 6c00 li a0,0
+ b8: R_MIPS16_HI16 \.bss\+0x1
+ bc: f400 3480 sll a0,16
+ c0: f000 4c00 addiu a0,0
+ c0: R_MIPS16_LO16 \.bss\+0x1
+ c4: f000 6c00 li a0,0
+ c4: R_MIPS16_HI16 \.sbss\+0x1
+ c8: f400 3480 sll a0,16
+ cc: f000 4c00 addiu a0,0
+ cc: R_MIPS16_LO16 \.sbss\+0x1
+ d0: 6c01 li a0,1
+ d2: f400 3480 sll a0,16
+ d6: f010 4c00 addiu a0,-32768
+ da: f000 6c00 li a0,0
+ da: R_MIPS16_HI16 \.data\+0x8000
+ de: f400 3480 sll a0,16
+ e2: f000 4c00 addiu a0,0
+ e2: R_MIPS16_LO16 \.data\+0x8000
+ e6: f000 6c00 li a0,0
+ e6: R_MIPS16_HI16 \.data\+0x8004
+ ea: f400 3480 sll a0,16
+ ee: f000 4c00 addiu a0,0
+ ee: R_MIPS16_LO16 \.data\+0x8004
+ f2: f000 6c00 li a0,0
+ f2: R_MIPS16_HI16 big_external_data_label\+0x8000
+ f6: f400 3480 sll a0,16
+ fa: f000 4c00 addiu a0,0
+ fa: R_MIPS16_LO16 big_external_data_label\+0x8000
+ fe: f000 6c00 li a0,0
+ fe: R_MIPS16_HI16 small_external_data_label\+0x8000
+ 102: f400 3480 sll a0,16
+ 106: f000 4c00 addiu a0,0
+ 106: R_MIPS16_LO16 small_external_data_label\+0x8000
+ 10a: f000 6c00 li a0,0
+ 10a: R_MIPS16_HI16 big_external_common\+0x8000
+ 10e: f400 3480 sll a0,16
+ 112: f000 4c00 addiu a0,0
+ 112: R_MIPS16_LO16 big_external_common\+0x8000
+ 116: f000 6c00 li a0,0
+ 116: R_MIPS16_HI16 small_external_common\+0x8000
+ 11a: f400 3480 sll a0,16
+ 11e: f000 4c00 addiu a0,0
+ 11e: R_MIPS16_LO16 small_external_common\+0x8000
+ 122: f000 6c00 li a0,0
+ 122: R_MIPS16_HI16 \.bss\+0x8000
+ 126: f400 3480 sll a0,16
+ 12a: f000 4c00 addiu a0,0
+ 12a: R_MIPS16_LO16 \.bss\+0x8000
+ 12e: f000 6c00 li a0,0
+ 12e: R_MIPS16_HI16 \.sbss\+0x8000
+ 132: f400 3480 sll a0,16
+ 136: f000 4c00 addiu a0,0
+ 136: R_MIPS16_LO16 \.sbss\+0x8000
+ 13a: 6c00 li a0,0
+ 13c: f400 3480 sll a0,16
+ 140: f010 4c00 addiu a0,-32768
+ 144: f000 6c00 li a0,0
+ 144: R_MIPS16_HI16 \.data\+0xffff8000
+ 148: f400 3480 sll a0,16
+ 14c: f000 4c00 addiu a0,0
+ 14c: R_MIPS16_LO16 \.data\+0xffff8000
+ 150: f000 6c00 li a0,0
+ 150: R_MIPS16_HI16 \.data\+0xffff8004
+ 154: f400 3480 sll a0,16
+ 158: f000 4c00 addiu a0,0
+ 158: R_MIPS16_LO16 \.data\+0xffff8004
+ 15c: f000 6c00 li a0,0
+ 15c: R_MIPS16_HI16 big_external_data_label\+0xffff8000
+ 160: f400 3480 sll a0,16
+ 164: f000 4c00 addiu a0,0
+ 164: R_MIPS16_LO16 big_external_data_label\+0xffff8000
+ 168: f000 6c00 li a0,0
+ 168: R_MIPS16_HI16 small_external_data_label\+0xffff8000
+ 16c: f400 3480 sll a0,16
+ 170: f000 4c00 addiu a0,0
+ 170: R_MIPS16_LO16 small_external_data_label\+0xffff8000
+ 174: f000 6c00 li a0,0
+ 174: R_MIPS16_HI16 big_external_common\+0xffff8000
+ 178: f400 3480 sll a0,16
+ 17c: f000 4c00 addiu a0,0
+ 17c: R_MIPS16_LO16 big_external_common\+0xffff8000
+ 180: f000 6c00 li a0,0
+ 180: R_MIPS16_HI16 small_external_common\+0xffff8000
+ 184: f400 3480 sll a0,16
+ 188: f000 4c00 addiu a0,0
+ 188: R_MIPS16_LO16 small_external_common\+0xffff8000
+ 18c: f000 6c00 li a0,0
+ 18c: R_MIPS16_HI16 \.bss\+0xffff8000
+ 190: f400 3480 sll a0,16
+ 194: f000 4c00 addiu a0,0
+ 194: R_MIPS16_LO16 \.bss\+0xffff8000
+ 198: f000 6c00 li a0,0
+ 198: R_MIPS16_HI16 \.sbss\+0xffff8000
+ 19c: f400 3480 sll a0,16
+ 1a0: f000 4c00 addiu a0,0
+ 1a0: R_MIPS16_LO16 \.sbss\+0xffff8000
+ 1a4: 6c01 li a0,1
+ 1a6: f400 3480 sll a0,16
+ 1aa: 4c00 addiu a0,0
+ 1ac: f000 6c00 li a0,0
+ 1ac: R_MIPS16_HI16 \.data\+0x10000
+ 1b0: f400 3480 sll a0,16
+ 1b4: f000 4c00 addiu a0,0
+ 1b4: R_MIPS16_LO16 \.data\+0x10000
+ 1b8: f000 6c00 li a0,0
+ 1b8: R_MIPS16_HI16 \.data\+0x10004
+ 1bc: f400 3480 sll a0,16
+ 1c0: f000 4c00 addiu a0,0
+ 1c0: R_MIPS16_LO16 \.data\+0x10004
+ 1c4: f000 6c00 li a0,0
+ 1c4: R_MIPS16_HI16 big_external_data_label\+0x10000
+ 1c8: f400 3480 sll a0,16
+ 1cc: f000 4c00 addiu a0,0
+ 1cc: R_MIPS16_LO16 big_external_data_label\+0x10000
+ 1d0: f000 6c00 li a0,0
+ 1d0: R_MIPS16_HI16 small_external_data_label\+0x10000
+ 1d4: f400 3480 sll a0,16
+ 1d8: f000 4c00 addiu a0,0
+ 1d8: R_MIPS16_LO16 small_external_data_label\+0x10000
+ 1dc: f000 6c00 li a0,0
+ 1dc: R_MIPS16_HI16 big_external_common\+0x10000
+ 1e0: f400 3480 sll a0,16
+ 1e4: f000 4c00 addiu a0,0
+ 1e4: R_MIPS16_LO16 big_external_common\+0x10000
+ 1e8: f000 6c00 li a0,0
+ 1e8: R_MIPS16_HI16 small_external_common\+0x10000
+ 1ec: f400 3480 sll a0,16
+ 1f0: f000 4c00 addiu a0,0
+ 1f0: R_MIPS16_LO16 small_external_common\+0x10000
+ 1f4: f000 6c00 li a0,0
+ 1f4: R_MIPS16_HI16 \.bss\+0x10000
+ 1f8: f400 3480 sll a0,16
+ 1fc: f000 4c00 addiu a0,0
+ 1fc: R_MIPS16_LO16 \.bss\+0x10000
+ 200: f000 6c00 li a0,0
+ 200: R_MIPS16_HI16 \.sbss\+0x10000
+ 204: f400 3480 sll a0,16
+ 208: f000 4c00 addiu a0,0
+ 208: R_MIPS16_LO16 \.sbss\+0x10000
+ 20c: 6c02 li a0,2
+ 20e: f400 3480 sll a0,16
+ 212: f5b4 4c05 addiu a0,-23131
+ 216: f000 6c00 li a0,0
+ 216: R_MIPS16_HI16 \.data\+0x1a5a5
+ 21a: f400 3480 sll a0,16
+ 21e: f000 4c00 addiu a0,0
+ 21e: R_MIPS16_LO16 \.data\+0x1a5a5
+ 222: f000 6c00 li a0,0
+ 222: R_MIPS16_HI16 \.data\+0x1a5a9
+ 226: f400 3480 sll a0,16
+ 22a: f000 4c00 addiu a0,0
+ 22a: R_MIPS16_LO16 \.data\+0x1a5a9
+ 22e: f000 6c00 li a0,0
+ 22e: R_MIPS16_HI16 big_external_data_label\+0x1a5a5
+ 232: f400 3480 sll a0,16
+ 236: f000 4c00 addiu a0,0
+ 236: R_MIPS16_LO16 big_external_data_label\+0x1a5a5
+ 23a: f000 6c00 li a0,0
+ 23a: R_MIPS16_HI16 small_external_data_label\+0x1a5a5
+ 23e: f400 3480 sll a0,16
+ 242: f000 4c00 addiu a0,0
+ 242: R_MIPS16_LO16 small_external_data_label\+0x1a5a5
+ 246: f000 6c00 li a0,0
+ 246: R_MIPS16_HI16 big_external_common\+0x1a5a5
+ 24a: f400 3480 sll a0,16
+ 24e: f000 4c00 addiu a0,0
+ 24e: R_MIPS16_LO16 big_external_common\+0x1a5a5
+ 252: f000 6c00 li a0,0
+ 252: R_MIPS16_HI16 small_external_common\+0x1a5a5
+ 256: f400 3480 sll a0,16
+ 25a: f000 4c00 addiu a0,0
+ 25a: R_MIPS16_LO16 small_external_common\+0x1a5a5
+ 25e: f000 6c00 li a0,0
+ 25e: R_MIPS16_HI16 \.bss\+0x1a5a5
+ 262: f400 3480 sll a0,16
+ 266: f000 4c00 addiu a0,0
+ 266: R_MIPS16_LO16 \.bss\+0x1a5a5
+ 26a: f000 6c00 li a0,0
+ 26a: R_MIPS16_HI16 \.sbss\+0x1a5a5
+ 26e: f400 3480 sll a0,16
+ 272: f000 4c00 addiu a0,0
+ 272: R_MIPS16_LO16 \.sbss\+0x1a5a5
+ 276: 6d00 li a1,0
+ 278: f400 35a0 sll a1,16
+ 27c: 9d80 lw a0,0\(a1\)
+ 27e: f000 6d00 li a1,0
+ 27e: R_MIPS16_HI16 \.data
+ 282: f400 35a0 sll a1,16
+ 286: f000 9d80 lw a0,0\(a1\)
+ 286: R_MIPS16_HI16 \.data
+ 28a: f000 6d00 li a1,0
+ 28a: R_MIPS16_HI16 \.data\+0x4
+ 28e: f400 35a0 sll a1,16
+ 292: f000 9d80 lw a0,0\(a1\)
+ 292: R_MIPS16_HI16 \.data\+0x4
+ 296: f000 6d00 li a1,0
+ 296: R_MIPS16_HI16 big_external_data_label
+ 29a: f400 35a0 sll a1,16
+ 29e: f000 9d80 lw a0,0\(a1\)
+ 29e: R_MIPS16_LO16 big_external_data_label
+ 2a2: f000 6d00 li a1,0
+ 2a2: R_MIPS16_HI16 small_external_data_label
+ 2a6: f400 35a0 sll a1,16
+ 2aa: f000 9d80 lw a0,0\(a1\)
+ 2aa: R_MIPS16_LO16 small_external_data_label
+ 2ae: f000 6d00 li a1,0
+ 2ae: R_MIPS16_HI16 big_external_common
+ 2b2: f400 35a0 sll a1,16
+ 2b6: f000 9d80 lw a0,0\(a1\)
+ 2b6: R_MIPS16_LO16 big_external_common
+ 2ba: f000 6d00 li a1,0
+ 2ba: R_MIPS16_HI16 small_external_common
+ 2be: f400 35a0 sll a1,16
+ 2c2: f000 9d80 lw a0,0\(a1\)
+ 2c2: R_MIPS16_LO16 small_external_common
+ 2c6: f000 6d00 li a1,0
+ 2c6: R_MIPS16_HI16 \.bss
+ 2ca: f400 35a0 sll a1,16
+ 2ce: f000 9d80 lw a0,0\(a1\)
+ 2ce: R_MIPS16_LO16 \.bss
+ 2d2: f000 6d00 li a1,0
+ 2d2: R_MIPS16_HI16 \.sbss
+ 2d6: f400 35a0 sll a1,16
+ 2da: f000 9d80 lw a0,0\(a1\)
+ 2da: R_MIPS16_LO16 \.sbss
+ 2de: 6d00 li a1,0
+ 2e0: f400 35a0 sll a1,16
+ 2e4: f000 9d81 lw a0,1\(a1\)
+ 2e8: f000 6d00 li a1,0
+ 2e8: R_MIPS16_HI16 \.data\+0x1
+ 2ec: f400 35a0 sll a1,16
+ 2f0: f000 9d80 lw a0,0\(a1\)
+ 2f0: R_MIPS16_LO16 \.data\+0x1
+ 2f4: f000 6d00 li a1,0
+ 2f4: R_MIPS16_HI16 \.data\+0x5
+ 2f8: f400 35a0 sll a1,16
+ 2fc: f000 9d80 lw a0,0\(a1\)
+ 2fc: R_MIPS16_LO16 \.data\+0x5
+ 300: f000 6d00 li a1,0
+ 300: R_MIPS16_HI16 big_external_data_label\+0x1
+ 304: f400 35a0 sll a1,16
+ 308: f000 9d80 lw a0,0\(a1\)
+ 308: R_MIPS16_LO16 big_external_data_label\+0x1
+ 30c: f000 6d00 li a1,0
+ 30c: R_MIPS16_HI16 small_external_data_label\+0x1
+ 310: f400 35a0 sll a1,16
+ 314: f000 9d80 lw a0,0\(a1\)
+ 314: R_MIPS16_LO16 small_external_data_label\+0x1
+ 318: f000 6d00 li a1,0
+ 318: R_MIPS16_HI16 big_external_common\+0x1
+ 31c: f400 35a0 sll a1,16
+ 320: f000 9d80 lw a0,0\(a1\)
+ 320: R_MIPS16_LO16 big_external_common\+0x1
+ 324: f000 6d00 li a1,0
+ 324: R_MIPS16_HI16 small_external_common\+0x1
+ 328: f400 35a0 sll a1,16
+ 32c: f000 9d80 lw a0,0\(a1\)
+ 32c: R_MIPS16_LO16 small_external_common\+0x1
+ 330: f000 6d00 li a1,0
+ 330: R_MIPS16_HI16 \.bss\+0x1
+ 334: f400 35a0 sll a1,16
+ 338: f000 9d80 lw a0,0\(a1\)
+ 338: R_MIPS16_LO16 \.bss\+0x1
+ 33c: f000 6d00 li a1,0
+ 33c: R_MIPS16_HI16 \.sbss\+0x1
+ 340: f400 35a0 sll a1,16
+ 344: f000 9d80 lw a0,0\(a1\)
+ 344: R_MIPS16_LO16 \.sbss\+0x1
+ 348: 6d01 li a1,1
+ 34a: f400 35a0 sll a1,16
+ 34e: f010 9d80 lw a0,-32768\(a1\)
+ 352: f000 6d00 li a1,0
+ 352: R_MIPS16_HI16 \.data\+0x8000
+ 356: f400 35a0 sll a1,16
+ 35a: f000 9d80 lw a0,0\(a1\)
+ 35a: R_MIPS16_LO16 \.data\+0x8000
+ 35e: f000 6d00 li a1,0
+ 35e: R_MIPS16_HI16 \.data\+0x8004
+ 362: f400 35a0 sll a1,16
+ 366: f000 9d80 lw a0,0\(a1\)
+ 366: R_MIPS16_LO16 \.data\+0x8004
+ 36a: f000 6d00 li a1,0
+ 36a: R_MIPS16_HI16 big_external_data_label\+0x8000
+ 36e: f400 35a0 sll a1,16
+ 372: f000 9d80 lw a0,0\(a1\)
+ 372: R_MIPS16_LO16 big_external_data_label\+0x8000
+ 376: f000 6d00 li a1,0
+ 376: R_MIPS16_HI16 small_external_data_label\+0x8000
+ 37a: f400 35a0 sll a1,16
+ 37e: f000 9d80 lw a0,0\(a1\)
+ 37e: R_MIPS16_LO16 small_external_data_label\+0x8000
+ 382: f000 6d00 li a1,0
+ 382: R_MIPS16_HI16 big_external_common\+0x8000
+ 386: f400 35a0 sll a1,16
+ 38a: f000 9d80 lw a0,0\(a1\)
+ 38a: R_MIPS16_LO16 big_external_common\+0x8000
+ 38e: f000 6d00 li a1,0
+ 38e: R_MIPS16_HI16 small_external_common\+0x8000
+ 392: f400 35a0 sll a1,16
+ 396: f000 9d80 lw a0,0\(a1\)
+ 396: R_MIPS16_LO16 small_external_common\+0x8000
+ 39a: f000 6d00 li a1,0
+ 39a: R_MIPS16_HI16 \.bss\+0x8000
+ 39e: f400 35a0 sll a1,16
+ 3a2: f000 9d80 lw a0,0\(a1\)
+ 3a2: R_MIPS16_LO16 \.bss\+0x8000
+ 3a6: f000 6d00 li a1,0
+ 3a6: R_MIPS16_HI16 \.sbss\+0x8000
+ 3aa: f400 35a0 sll a1,16
+ 3ae: f000 9d80 lw a0,0\(a1\)
+ 3ae: R_MIPS16_LO16 \.sbss\+0x8000
+ 3b2: 6d00 li a1,0
+ 3b4: f400 35a0 sll a1,16
+ 3b8: f010 9d80 lw a0,-32768\(a1\)
+ 3bc: f000 6d00 li a1,0
+ 3bc: R_MIPS16_HI16 \.data\+0xffff8000
+ 3c0: f400 35a0 sll a1,16
+ 3c4: f000 9d80 lw a0,0\(a1\)
+ 3c4: R_MIPS16_LO16 \.data\+0xffff8000
+ 3c8: f000 6d00 li a1,0
+ 3c8: R_MIPS16_HI16 \.data\+0xffff8004
+ 3cc: f400 35a0 sll a1,16
+ 3d0: f000 9d80 lw a0,0\(a1\)
+ 3d0: R_MIPS16_LO16 \.data\+0xffff8004
+ 3d4: f000 6d00 li a1,0
+ 3d4: R_MIPS16_HI16 big_external_data_label\+0xffff8000
+ 3d8: f400 35a0 sll a1,16
+ 3dc: f000 9d80 lw a0,0\(a1\)
+ 3dc: R_MIPS16_LO16 big_external_data_label\+0xffff8000
+ 3e0: f000 6d00 li a1,0
+ 3e0: R_MIPS16_HI16 small_external_data_label\+0xffff8000
+ 3e4: f400 35a0 sll a1,16
+ 3e8: f000 9d80 lw a0,0\(a1\)
+ 3e8: R_MIPS16_LO16 small_external_data_label\+0xffff8000
+ 3ec: f000 6d00 li a1,0
+ 3ec: R_MIPS16_HI16 big_external_common\+0xffff8000
+ 3f0: f400 35a0 sll a1,16
+ 3f4: f000 9d80 lw a0,0\(a1\)
+ 3f4: R_MIPS16_LO16 big_external_common\+0xffff8000
+ 3f8: f000 6d00 li a1,0
+ 3f8: R_MIPS16_HI16 small_external_common\+0xffff8000
+ 3fc: f400 35a0 sll a1,16
+ 400: f000 9d80 lw a0,0\(a1\)
+ 400: R_MIPS16_LO16 small_external_common\+0xffff8000
+ 404: f000 6d00 li a1,0
+ 404: R_MIPS16_HI16 \.bss\+0xffff8000
+ 408: f400 35a0 sll a1,16
+ 40c: f000 9d80 lw a0,0\(a1\)
+ 40c: R_MIPS16_LO16 \.bss\+0xffff8000
+ 410: f000 6d00 li a1,0
+ 410: R_MIPS16_HI16 \.sbss\+0xffff8000
+ 414: f400 35a0 sll a1,16
+ 418: f000 9d80 lw a0,0\(a1\)
+ 418: R_MIPS16_LO16 \.sbss\+0xffff8000
+ 41c: 6d01 li a1,1
+ 41e: f400 35a0 sll a1,16
+ 422: 9d80 lw a0,0\(a1\)
+ 424: f000 6d00 li a1,0
+ 424: R_MIPS16_HI16 \.data\+0x10000
+ 428: f400 35a0 sll a1,16
+ 42c: f000 9d80 lw a0,0\(a1\)
+ 42c: R_MIPS16_LO16 \.data\+0x10000
+ 430: f000 6d00 li a1,0
+ 430: R_MIPS16_HI16 \.data\+0x10004
+ 434: f400 35a0 sll a1,16
+ 438: f000 9d80 lw a0,0\(a1\)
+ 438: R_MIPS16_LO16 \.data\+0x10004
+ 43c: f000 6d00 li a1,0
+ 43c: R_MIPS16_HI16 big_external_data_label\+0x10000
+ 440: f400 35a0 sll a1,16
+ 444: f000 9d80 lw a0,0\(a1\)
+ 444: R_MIPS16_LO16 big_external_data_label\+0x10000
+ 448: f000 6d00 li a1,0
+ 448: R_MIPS16_HI16 small_external_data_label\+0x10000
+ 44c: f400 35a0 sll a1,16
+ 450: f000 9d80 lw a0,0\(a1\)
+ 450: R_MIPS16_LO16 small_external_data_label\+0x10000
+ 454: f000 6d00 li a1,0
+ 454: R_MIPS16_HI16 big_external_common\+0x10000
+ 458: f400 35a0 sll a1,16
+ 45c: f000 9d80 lw a0,0\(a1\)
+ 45c: R_MIPS16_LO16 big_external_common\+0x10000
+ 460: f000 6d00 li a1,0
+ 460: R_MIPS16_HI16 small_external_common\+0x10000
+ 464: f400 35a0 sll a1,16
+ 468: f000 9d80 lw a0,0\(a1\)
+ 468: R_MIPS16_LO16 small_external_common\+0x10000
+ 46c: f000 6d00 li a1,0
+ 46c: R_MIPS16_HI16 \.bss\+0x10000
+ 470: f400 35a0 sll a1,16
+ 474: f000 9d80 lw a0,0\(a1\)
+ 474: R_MIPS16_LO16 \.bss\+0x10000
+ 478: f000 6d00 li a1,0
+ 478: R_MIPS16_HI16 \.sbss\+0x10000
+ 47c: f400 35a0 sll a1,16
+ 480: f000 9d80 lw a0,0\(a1\)
+ 480: R_MIPS16_LO16 \.sbss\+0x10000
+ 484: 6d02 li a1,2
+ 486: f400 35a0 sll a1,16
+ 48a: f5b4 9d85 lw a0,-23131\(a1\)
+ 48e: f000 6d00 li a1,0
+ 48e: R_MIPS16_HI16 \.data\+0x1a5a5
+ 492: f400 35a0 sll a1,16
+ 496: f000 9d80 lw a0,0\(a1\)
+ 496: R_MIPS16_LO16 \.data\+0x1a5a5
+ 49a: f000 6d00 li a1,0
+ 49a: R_MIPS16_HI16 \.data\+0x1a5a9
+ 49e: f400 35a0 sll a1,16
+ 4a2: f000 9d80 lw a0,0\(a1\)
+ 4a2: R_MIPS16_LO16 \.data\+0x1a5a9
+ 4a6: f000 6d00 li a1,0
+ 4a6: R_MIPS16_HI16 big_external_data_label\+0x1a5a5
+ 4aa: f400 35a0 sll a1,16
+ 4ae: f000 9d80 lw a0,0\(a1\)
+ 4ae: R_MIPS16_LO16 big_external_data_label\+0x1a5a5
+ 4b2: f000 6d00 li a1,0
+ 4b2: R_MIPS16_HI16 small_external_data_label\+0x1a5a5
+ 4b6: f400 35a0 sll a1,16
+ 4ba: f000 9d80 lw a0,0\(a1\)
+ 4ba: R_MIPS16_LO16 small_external_data_label\+0x1a5a5
+ 4be: f000 6d00 li a1,0
+ 4be: R_MIPS16_HI16 big_external_common\+0x1a5a5
+ 4c2: f400 35a0 sll a1,16
+ 4c6: f000 9d80 lw a0,0\(a1\)
+ 4c6: R_MIPS16_LO16 big_external_common\+0x1a5a5
+ 4ca: f000 6d00 li a1,0
+ 4ca: R_MIPS16_HI16 small_external_common\+0x1a5a5
+ 4ce: f400 35a0 sll a1,16
+ 4d2: f000 9d80 lw a0,0\(a1\)
+ 4d2: R_MIPS16_LO16 small_external_common\+0x1a5a5
+ 4d6: f000 6d00 li a1,0
+ 4d6: R_MIPS16_HI16 \.bss\+0x1a5a5
+ 4da: f400 35a0 sll a1,16
+ 4de: f000 9d80 lw a0,0\(a1\)
+ 4de: R_MIPS16_LO16 \.bss\+0x1a5a5
+ 4e2: f000 6d00 li a1,0
+ 4e2: R_MIPS16_HI16 \.sbss\+0x1a5a5
+ 4e6: f400 35a0 sll a1,16
+ 4ea: f000 9d80 lw a0,0\(a1\)
+ 4ea: R_MIPS16_LO16 \.sbss\+0x1a5a5
+ 4ee: 6500 nop
diff -up --recursive --new-file binutils-2.15.94-20050214.macro/gas/testsuite/gas/mips/mips16-hilo.d binutils-2.15.94-20050214/gas/testsuite/gas/mips/mips16-hilo.d
--- binutils-2.15.94-20050214.macro/gas/testsuite/gas/mips/mips16-hilo.d 1970-01-01 00:00:00.000000000 +0000
+++ binutils-2.15.94-20050214/gas/testsuite/gas/mips/mips16-hilo.d 2005-02-11 23:44:58.000000000 +0000
@@ -0,0 +1,527 @@
+#objdump: -dr
+#name: MIPS16 lui/addi
+#as: -mips16 -mabi=32
+#source: mips16-hilo.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+0+0000 <stuff>:
+ 0: 6c00 li a0,0
+ 2: f400 3480 sll a0,16
+ 6: 4c00 addiu a0,0
+ 8: f000 6c00 li a0,0
+ 8: R_MIPS16_HI16 \.data
+ c: f400 3480 sll a0,16
+ 10: f000 4c00 addiu a0,0
+ 10: R_MIPS16_LO16 \.data
+ 14: f000 6c00 li a0,0
+ 14: R_MIPS16_HI16 \.data
+ 18: f400 3480 sll a0,16
+ 1c: f000 4c04 addiu a0,4
+ 1c: R_MIPS16_LO16 \.data
+ 20: f000 6c00 li a0,0
+ 20: R_MIPS16_HI16 big_external_data_label
+ 24: f400 3480 sll a0,16
+ 28: f000 4c00 addiu a0,0
+ 28: R_MIPS16_LO16 big_external_data_label
+ 2c: f000 6c00 li a0,0
+ 2c: R_MIPS16_HI16 small_external_data_label
+ 30: f400 3480 sll a0,16
+ 34: f000 4c00 addiu a0,0
+ 34: R_MIPS16_LO16 small_external_data_label
+ 38: f000 6c00 li a0,0
+ 38: R_MIPS16_HI16 big_external_common
+ 3c: f400 3480 sll a0,16
+ 40: f000 4c00 addiu a0,0
+ 40: R_MIPS16_LO16 big_external_common
+ 44: f000 6c00 li a0,0
+ 44: R_MIPS16_HI16 small_external_common
+ 48: f400 3480 sll a0,16
+ 4c: f000 4c00 addiu a0,0
+ 4c: R_MIPS16_LO16 small_external_common
+ 50: f000 6c00 li a0,0
+ 50: R_MIPS16_HI16 \.bss
+ 54: f400 3480 sll a0,16
+ 58: f000 4c00 addiu a0,0
+ 58: R_MIPS16_LO16 \.bss
+ 5c: f000 6c00 li a0,0
+ 5c: R_MIPS16_HI16 \.sbss
+ 60: f400 3480 sll a0,16
+ 64: f000 4c00 addiu a0,0
+ 64: R_MIPS16_LO16 \.sbss
+ 68: 6c00 li a0,0
+ 6a: f400 3480 sll a0,16
+ 6e: 4c01 addiu a0,1
+ 70: f000 6c00 li a0,0
+ 70: R_MIPS16_HI16 \.data
+ 74: f400 3480 sll a0,16
+ 78: f000 4c01 addiu a0,1
+ 78: R_MIPS16_LO16 \.data
+ 7c: f000 6c00 li a0,0
+ 7c: R_MIPS16_HI16 \.data
+ 80: f400 3480 sll a0,16
+ 84: f000 4c05 addiu a0,5
+ 84: R_MIPS16_LO16 \.data
+ 88: f000 6c00 li a0,0
+ 88: R_MIPS16_HI16 big_external_data_label
+ 8c: f400 3480 sll a0,16
+ 90: f000 4c01 addiu a0,1
+ 90: R_MIPS16_LO16 big_external_data_label
+ 94: f000 6c00 li a0,0
+ 94: R_MIPS16_HI16 small_external_data_label
+ 98: f400 3480 sll a0,16
+ 9c: f000 4c01 addiu a0,1
+ 9c: R_MIPS16_LO16 small_external_data_label
+ a0: f000 6c00 li a0,0
+ a0: R_MIPS16_HI16 big_external_common
+ a4: f400 3480 sll a0,16
+ a8: f000 4c01 addiu a0,1
+ a8: R_MIPS16_LO16 big_external_common
+ ac: f000 6c00 li a0,0
+ ac: R_MIPS16_HI16 small_external_common
+ b0: f400 3480 sll a0,16
+ b4: f000 4c01 addiu a0,1
+ b4: R_MIPS16_LO16 small_external_common
+ b8: f000 6c00 li a0,0
+ b8: R_MIPS16_HI16 \.bss
+ bc: f400 3480 sll a0,16
+ c0: f000 4c01 addiu a0,1
+ c0: R_MIPS16_LO16 \.bss
+ c4: f000 6c00 li a0,0
+ c4: R_MIPS16_HI16 \.sbss
+ c8: f400 3480 sll a0,16
+ cc: f000 4c01 addiu a0,1
+ cc: R_MIPS16_LO16 \.sbss
+ d0: 6c01 li a0,1
+ d2: f400 3480 sll a0,16
+ d6: f010 4c00 addiu a0,-32768
+ da: f000 6c01 li a0,1
+ da: R_MIPS16_HI16 \.data
+ de: f400 3480 sll a0,16
+ e2: f010 4c00 addiu a0,-32768
+ e2: R_MIPS16_LO16 \.data
+ e6: f000 6c01 li a0,1
+ e6: R_MIPS16_HI16 \.data
+ ea: f400 3480 sll a0,16
+ ee: f010 4c04 addiu a0,-32764
+ ee: R_MIPS16_LO16 \.data
+ f2: f000 6c01 li a0,1
+ f2: R_MIPS16_HI16 big_external_data_label
+ f6: f400 3480 sll a0,16
+ fa: f010 4c00 addiu a0,-32768
+ fa: R_MIPS16_LO16 big_external_data_label
+ fe: f000 6c01 li a0,1
+ fe: R_MIPS16_HI16 small_external_data_label
+ 102: f400 3480 sll a0,16
+ 106: f010 4c00 addiu a0,-32768
+ 106: R_MIPS16_LO16 small_external_data_label
+ 10a: f000 6c01 li a0,1
+ 10a: R_MIPS16_HI16 big_external_common
+ 10e: f400 3480 sll a0,16
+ 112: f010 4c00 addiu a0,-32768
+ 112: R_MIPS16_LO16 big_external_common
+ 116: f000 6c01 li a0,1
+ 116: R_MIPS16_HI16 small_external_common
+ 11a: f400 3480 sll a0,16
+ 11e: f010 4c00 addiu a0,-32768
+ 11e: R_MIPS16_LO16 small_external_common
+ 122: f000 6c01 li a0,1
+ 122: R_MIPS16_HI16 \.bss
+ 126: f400 3480 sll a0,16
+ 12a: f010 4c00 addiu a0,-32768
+ 12a: R_MIPS16_LO16 \.bss
+ 12e: f000 6c01 li a0,1
+ 12e: R_MIPS16_HI16 \.sbss
+ 132: f400 3480 sll a0,16
+ 136: f010 4c00 addiu a0,-32768
+ 136: R_MIPS16_LO16 \.sbss
+ 13a: 6c00 li a0,0
+ 13c: f400 3480 sll a0,16
+ 140: f010 4c00 addiu a0,-32768
+ 144: f000 6c00 li a0,0
+ 144: R_MIPS16_HI16 \.data
+ 148: f400 3480 sll a0,16
+ 14c: f010 4c00 addiu a0,-32768
+ 14c: R_MIPS16_LO16 \.data
+ 150: f000 6c00 li a0,0
+ 150: R_MIPS16_HI16 \.data
+ 154: f400 3480 sll a0,16
+ 158: f010 4c04 addiu a0,-32764
+ 158: R_MIPS16_LO16 \.data
+ 15c: f000 6c00 li a0,0
+ 15c: R_MIPS16_HI16 big_external_data_label
+ 160: f400 3480 sll a0,16
+ 164: f010 4c00 addiu a0,-32768
+ 164: R_MIPS16_LO16 big_external_data_label
+ 168: f000 6c00 li a0,0
+ 168: R_MIPS16_HI16 small_external_data_label
+ 16c: f400 3480 sll a0,16
+ 170: f010 4c00 addiu a0,-32768
+ 170: R_MIPS16_LO16 small_external_data_label
+ 174: f000 6c00 li a0,0
+ 174: R_MIPS16_HI16 big_external_common
+ 178: f400 3480 sll a0,16
+ 17c: f010 4c00 addiu a0,-32768
+ 17c: R_MIPS16_LO16 big_external_common
+ 180: f000 6c00 li a0,0
+ 180: R_MIPS16_HI16 small_external_common
+ 184: f400 3480 sll a0,16
+ 188: f010 4c00 addiu a0,-32768
+ 188: R_MIPS16_LO16 small_external_common
+ 18c: f000 6c00 li a0,0
+ 18c: R_MIPS16_HI16 \.bss
+ 190: f400 3480 sll a0,16
+ 194: f010 4c00 addiu a0,-32768
+ 194: R_MIPS16_LO16 \.bss
+ 198: f000 6c00 li a0,0
+ 198: R_MIPS16_HI16 \.sbss
+ 19c: f400 3480 sll a0,16
+ 1a0: f010 4c00 addiu a0,-32768
+ 1a0: R_MIPS16_LO16 \.sbss
+ 1a4: 6c01 li a0,1
+ 1a6: f400 3480 sll a0,16
+ 1aa: 4c00 addiu a0,0
+ 1ac: f000 6c01 li a0,1
+ 1ac: R_MIPS16_HI16 \.data
+ 1b0: f400 3480 sll a0,16
+ 1b4: f000 4c00 addiu a0,0
+ 1b4: R_MIPS16_LO16 \.data
+ 1b8: f000 6c01 li a0,1
+ 1b8: R_MIPS16_HI16 \.data
+ 1bc: f400 3480 sll a0,16
+ 1c0: f000 4c04 addiu a0,4
+ 1c0: R_MIPS16_LO16 \.data
+ 1c4: f000 6c01 li a0,1
+ 1c4: R_MIPS16_HI16 big_external_data_label
+ 1c8: f400 3480 sll a0,16
+ 1cc: f000 4c00 addiu a0,0
+ 1cc: R_MIPS16_LO16 big_external_data_label
+ 1d0: f000 6c01 li a0,1
+ 1d0: R_MIPS16_HI16 small_external_data_label
+ 1d4: f400 3480 sll a0,16
+ 1d8: f000 4c00 addiu a0,0
+ 1d8: R_MIPS16_LO16 small_external_data_label
+ 1dc: f000 6c01 li a0,1
+ 1dc: R_MIPS16_HI16 big_external_common
+ 1e0: f400 3480 sll a0,16
+ 1e4: f000 4c00 addiu a0,0
+ 1e4: R_MIPS16_LO16 big_external_common
+ 1e8: f000 6c01 li a0,1
+ 1e8: R_MIPS16_HI16 small_external_common
+ 1ec: f400 3480 sll a0,16
+ 1f0: f000 4c00 addiu a0,0
+ 1f0: R_MIPS16_LO16 small_external_common
+ 1f4: f000 6c01 li a0,1
+ 1f4: R_MIPS16_HI16 \.bss
+ 1f8: f400 3480 sll a0,16
+ 1fc: f000 4c00 addiu a0,0
+ 1fc: R_MIPS16_LO16 \.bss
+ 200: f000 6c01 li a0,1
+ 200: R_MIPS16_HI16 \.sbss
+ 204: f400 3480 sll a0,16
+ 208: f000 4c00 addiu a0,0
+ 208: R_MIPS16_LO16 \.sbss
+ 20c: 6c02 li a0,2
+ 20e: f400 3480 sll a0,16
+ 212: f5b4 4c05 addiu a0,-23131
+ 216: f000 6c02 li a0,2
+ 216: R_MIPS16_HI16 \.data
+ 21a: f400 3480 sll a0,16
+ 21e: f5b4 4c05 addiu a0,-23131
+ 21e: R_MIPS16_LO16 \.data
+ 222: f000 6c02 li a0,2
+ 222: R_MIPS16_HI16 \.data
+ 226: f400 3480 sll a0,16
+ 22a: f5b4 4c09 addiu a0,-23127
+ 22a: R_MIPS16_LO16 \.data
+ 22e: f000 6c02 li a0,2
+ 22e: R_MIPS16_HI16 big_external_data_label
+ 232: f400 3480 sll a0,16
+ 236: f5b4 4c05 addiu a0,-23131
+ 236: R_MIPS16_LO16 big_external_data_label
+ 23a: f000 6c02 li a0,2
+ 23a: R_MIPS16_HI16 small_external_data_label
+ 23e: f400 3480 sll a0,16
+ 242: f5b4 4c05 addiu a0,-23131
+ 242: R_MIPS16_LO16 small_external_data_label
+ 246: f000 6c02 li a0,2
+ 246: R_MIPS16_HI16 big_external_common
+ 24a: f400 3480 sll a0,16
+ 24e: f5b4 4c05 addiu a0,-23131
+ 24e: R_MIPS16_LO16 big_external_common
+ 252: f000 6c02 li a0,2
+ 252: R_MIPS16_HI16 small_external_common
+ 256: f400 3480 sll a0,16
+ 25a: f5b4 4c05 addiu a0,-23131
+ 25a: R_MIPS16_LO16 small_external_common
+ 25e: f000 6c02 li a0,2
+ 25e: R_MIPS16_HI16 \.bss
+ 262: f400 3480 sll a0,16
+ 266: f5b4 4c05 addiu a0,-23131
+ 266: R_MIPS16_LO16 \.bss
+ 26a: f000 6c02 li a0,2
+ 26a: R_MIPS16_HI16 \.sbss
+ 26e: f400 3480 sll a0,16
+ 272: f5b4 4c05 addiu a0,-23131
+ 272: R_MIPS16_LO16 \.sbss
+ 276: 6d00 li a1,0
+ 278: f400 35a0 sll a1,16
+ 27c: 9d80 lw a0,0\(a1\)
+ 27e: f000 6d00 li a1,0
+ 27e: R_MIPS16_HI16 \.data
+ 282: f400 35a0 sll a1,16
+ 286: f000 9d80 lw a0,0\(a1\)
+ 286: R_MIPS16_HI16 \.data
+ 28a: f000 6d00 li a1,0
+ 28a: R_MIPS16_HI16 \.data
+ 28e: f400 35a0 sll a1,16
+ 292: f000 9d80 lw a0,0\(a1\)
+ 292: R_MIPS16_HI16 \.data
+ 296: f000 6d00 li a1,0
+ 296: R_MIPS16_HI16 big_external_data_label
+ 29a: f400 35a0 sll a1,16
+ 29e: f000 9d80 lw a0,0\(a1\)
+ 29e: R_MIPS16_LO16 big_external_data_label
+ 2a2: f000 6d00 li a1,0
+ 2a2: R_MIPS16_HI16 small_external_data_label
+ 2a6: f400 35a0 sll a1,16
+ 2aa: f000 9d80 lw a0,0\(a1\)
+ 2aa: R_MIPS16_LO16 small_external_data_label
+ 2ae: f000 6d00 li a1,0
+ 2ae: R_MIPS16_HI16 big_external_common
+ 2b2: f400 35a0 sll a1,16
+ 2b6: f000 9d80 lw a0,0\(a1\)
+ 2b6: R_MIPS16_LO16 big_external_common
+ 2ba: f000 6d00 li a1,0
+ 2ba: R_MIPS16_HI16 small_external_common
+ 2be: f400 35a0 sll a1,16
+ 2c2: f000 9d80 lw a0,0\(a1\)
+ 2c2: R_MIPS16_LO16 small_external_common
+ 2c6: f000 6d00 li a1,0
+ 2c6: R_MIPS16_HI16 \.bss
+ 2ca: f400 35a0 sll a1,16
+ 2ce: f000 9d80 lw a0,0\(a1\)
+ 2ce: R_MIPS16_LO16 \.bss
+ 2d2: f000 6d00 li a1,0
+ 2d2: R_MIPS16_HI16 \.sbss
+ 2d6: f400 35a0 sll a1,16
+ 2da: f000 9d80 lw a0,0\(a1\)
+ 2da: R_MIPS16_LO16 \.sbss
+ 2de: 6d00 li a1,0
+ 2e0: f400 35a0 sll a1,16
+ 2e4: f000 9d81 lw a0,1\(a1\)
+ 2e8: f000 6d00 li a1,0
+ 2e8: R_MIPS16_HI16 \.data
+ 2ec: f400 35a0 sll a1,16
+ 2f0: f000 9d81 lw a0,1\(a1\)
+ 2f0: R_MIPS16_LO16 \.data
+ 2f4: f000 6d00 li a1,0
+ 2f4: R_MIPS16_HI16 \.data
+ 2f8: f400 35a0 sll a1,16
+ 2fc: f000 9d85 lw a0,5\(a1\)
+ 2fc: R_MIPS16_LO16 \.data
+ 300: f000 6d00 li a1,0
+ 300: R_MIPS16_HI16 big_external_data_label
+ 304: f400 35a0 sll a1,16
+ 308: f000 9d81 lw a0,1\(a1\)
+ 308: R_MIPS16_LO16 big_external_data_label
+ 30c: f000 6d00 li a1,0
+ 30c: R_MIPS16_HI16 small_external_data_label
+ 310: f400 35a0 sll a1,16
+ 314: f000 9d81 lw a0,1\(a1\)
+ 314: R_MIPS16_LO16 small_external_data_label
+ 318: f000 6d00 li a1,0
+ 318: R_MIPS16_HI16 big_external_common
+ 31c: f400 35a0 sll a1,16
+ 320: f000 9d81 lw a0,1\(a1\)
+ 320: R_MIPS16_LO16 big_external_common
+ 324: f000 6d00 li a1,0
+ 324: R_MIPS16_HI16 small_external_common
+ 328: f400 35a0 sll a1,16
+ 32c: f000 9d81 lw a0,1\(a1\)
+ 32c: R_MIPS16_LO16 small_external_common
+ 330: f000 6d00 li a1,0
+ 330: R_MIPS16_HI16 \.bss
+ 334: f400 35a0 sll a1,16
+ 338: f000 9d81 lw a0,1\(a1\)
+ 338: R_MIPS16_LO16 \.bss
+ 33c: f000 6d00 li a1,0
+ 33c: R_MIPS16_HI16 \.sbss
+ 340: f400 35a0 sll a1,16
+ 344: f000 9d81 lw a0,1\(a1\)
+ 344: R_MIPS16_LO16 \.sbss
+ 348: 6d01 li a1,1
+ 34a: f400 35a0 sll a1,16
+ 34e: f010 9d80 lw a0,-32768\(a1\)
+ 352: f000 6d01 li a1,1
+ 352: R_MIPS16_HI16 \.data
+ 356: f400 35a0 sll a1,16
+ 35a: f010 9d80 lw a0,-32768\(a1\)
+ 35a: R_MIPS16_LO16 \.data
+ 35e: f000 6d01 li a1,1
+ 35e: R_MIPS16_HI16 \.data
+ 362: f400 35a0 sll a1,16
+ 366: f010 9d84 lw a0,-32764\(a1\)
+ 366: R_MIPS16_LO16 \.data
+ 36a: f000 6d01 li a1,1
+ 36a: R_MIPS16_HI16 big_external_data_label
+ 36e: f400 35a0 sll a1,16
+ 372: f010 9d80 lw a0,-32768\(a1\)
+ 372: R_MIPS16_LO16 big_external_data_label
+ 376: f000 6d01 li a1,1
+ 376: R_MIPS16_HI16 small_external_data_label
+ 37a: f400 35a0 sll a1,16
+ 37e: f010 9d80 lw a0,-32768\(a1\)
+ 37e: R_MIPS16_LO16 small_external_data_label
+ 382: f000 6d01 li a1,1
+ 382: R_MIPS16_HI16 big_external_common
+ 386: f400 35a0 sll a1,16
+ 38a: f010 9d80 lw a0,-32768\(a1\)
+ 38a: R_MIPS16_LO16 big_external_common
+ 38e: f000 6d01 li a1,1
+ 38e: R_MIPS16_HI16 small_external_common
+ 392: f400 35a0 sll a1,16
+ 396: f010 9d80 lw a0,-32768\(a1\)
+ 396: R_MIPS16_LO16 small_external_common
+ 39a: f000 6d01 li a1,1
+ 39a: R_MIPS16_HI16 \.bss
+ 39e: f400 35a0 sll a1,16
+ 3a2: f010 9d80 lw a0,-32768\(a1\)
+ 3a2: R_MIPS16_LO16 \.bss
+ 3a6: f000 6d01 li a1,1
+ 3a6: R_MIPS16_HI16 \.sbss
+ 3aa: f400 35a0 sll a1,16
+ 3ae: f010 9d80 lw a0,-32768\(a1\)
+ 3ae: R_MIPS16_LO16 \.sbss
+ 3b2: 6d00 li a1,0
+ 3b4: f400 35a0 sll a1,16
+ 3b8: f010 9d80 lw a0,-32768\(a1\)
+ 3bc: f000 6d00 li a1,0
+ 3bc: R_MIPS16_HI16 \.data
+ 3c0: f400 35a0 sll a1,16
+ 3c4: f010 9d80 lw a0,-32768\(a1\)
+ 3c4: R_MIPS16_LO16 \.data
+ 3c8: f000 6d00 li a1,0
+ 3c8: R_MIPS16_HI16 \.data
+ 3cc: f400 35a0 sll a1,16
+ 3d0: f010 9d84 lw a0,-32764\(a1\)
+ 3d0: R_MIPS16_LO16 \.data
+ 3d4: f000 6d00 li a1,0
+ 3d4: R_MIPS16_HI16 big_external_data_label
+ 3d8: f400 35a0 sll a1,16
+ 3dc: f010 9d80 lw a0,-32768\(a1\)
+ 3dc: R_MIPS16_LO16 big_external_data_label
+ 3e0: f000 6d00 li a1,0
+ 3e0: R_MIPS16_HI16 small_external_data_label
+ 3e4: f400 35a0 sll a1,16
+ 3e8: f010 9d80 lw a0,-32768\(a1\)
+ 3e8: R_MIPS16_LO16 small_external_data_label
+ 3ec: f000 6d00 li a1,0
+ 3ec: R_MIPS16_HI16 big_external_common
+ 3f0: f400 35a0 sll a1,16
+ 3f4: f010 9d80 lw a0,-32768\(a1\)
+ 3f4: R_MIPS16_LO16 big_external_common
+ 3f8: f000 6d00 li a1,0
+ 3f8: R_MIPS16_HI16 small_external_common
+ 3fc: f400 35a0 sll a1,16
+ 400: f010 9d80 lw a0,-32768\(a1\)
+ 400: R_MIPS16_LO16 small_external_common
+ 404: f000 6d00 li a1,0
+ 404: R_MIPS16_HI16 \.bss
+ 408: f400 35a0 sll a1,16
+ 40c: f010 9d80 lw a0,-32768\(a1\)
+ 40c: R_MIPS16_LO16 \.bss
+ 410: f000 6d00 li a1,0
+ 410: R_MIPS16_HI16 \.sbss
+ 414: f400 35a0 sll a1,16
+ 418: f010 9d80 lw a0,-32768\(a1\)
+ 418: R_MIPS16_LO16 \.sbss
+ 41c: 6d01 li a1,1
+ 41e: f400 35a0 sll a1,16
+ 422: 9d80 lw a0,0\(a1\)
+ 424: f000 6d01 li a1,1
+ 424: R_MIPS16_HI16 \.data
+ 428: f400 35a0 sll a1,16
+ 42c: f000 9d80 lw a0,0\(a1\)
+ 42c: R_MIPS16_LO16 \.data
+ 430: f000 6d01 li a1,1
+ 430: R_MIPS16_HI16 \.data
+ 434: f400 35a0 sll a1,16
+ 438: f000 9d84 lw a0,4\(a1\)
+ 438: R_MIPS16_LO16 \.data
+ 43c: f000 6d01 li a1,1
+ 43c: R_MIPS16_HI16 big_external_data_label
+ 440: f400 35a0 sll a1,16
+ 444: f000 9d80 lw a0,0\(a1\)
+ 444: R_MIPS16_LO16 big_external_data_label
+ 448: f000 6d01 li a1,1
+ 448: R_MIPS16_HI16 small_external_data_label
+ 44c: f400 35a0 sll a1,16
+ 450: f000 9d80 lw a0,0\(a1\)
+ 450: R_MIPS16_LO16 small_external_data_label
+ 454: f000 6d01 li a1,1
+ 454: R_MIPS16_HI16 big_external_common
+ 458: f400 35a0 sll a1,16
+ 45c: f000 9d80 lw a0,0\(a1\)
+ 45c: R_MIPS16_LO16 big_external_common
+ 460: f000 6d01 li a1,1
+ 460: R_MIPS16_HI16 small_external_common
+ 464: f400 35a0 sll a1,16
+ 468: f000 9d80 lw a0,0\(a1\)
+ 468: R_MIPS16_LO16 small_external_common
+ 46c: f000 6d01 li a1,1
+ 46c: R_MIPS16_HI16 \.bss
+ 470: f400 35a0 sll a1,16
+ 474: f000 9d80 lw a0,0\(a1\)
+ 474: R_MIPS16_LO16 \.bss
+ 478: f000 6d01 li a1,1
+ 478: R_MIPS16_HI16 \.sbss
+ 47c: f400 35a0 sll a1,16
+ 480: f000 9d80 lw a0,0\(a1\)
+ 480: R_MIPS16_LO16 \.sbss
+ 484: 6d02 li a1,2
+ 486: f400 35a0 sll a1,16
+ 48a: f5b4 9d85 lw a0,-23131\(a1\)
+ 48e: f000 6d02 li a1,2
+ 48e: R_MIPS16_HI16 \.data
+ 492: f400 35a0 sll a1,16
+ 496: f5b4 9d85 lw a0,-23131\(a1\)
+ 496: R_MIPS16_LO16 \.data
+ 49a: f000 6d02 li a1,2
+ 49a: R_MIPS16_HI16 \.data
+ 49e: f400 35a0 sll a1,16
+ 4a2: f5b4 9d89 lw a0,-23127\(a1\)
+ 4a2: R_MIPS16_LO16 \.data
+ 4a6: f000 6d02 li a1,2
+ 4a6: R_MIPS16_HI16 big_external_data_label
+ 4aa: f400 35a0 sll a1,16
+ 4ae: f5b4 9d85 lw a0,-23131\(a1\)
+ 4ae: R_MIPS16_LO16 big_external_data_label
+ 4b2: f000 6d02 li a1,2
+ 4b2: R_MIPS16_HI16 small_external_data_label
+ 4b6: f400 35a0 sll a1,16
+ 4ba: f5b4 9d85 lw a0,-23131\(a1\)
+ 4ba: R_MIPS16_LO16 small_external_data_label
+ 4be: f000 6d02 li a1,2
+ 4be: R_MIPS16_HI16 big_external_common
+ 4c2: f400 35a0 sll a1,16
+ 4c6: f5b4 9d85 lw a0,-23131\(a1\)
+ 4c6: R_MIPS16_LO16 big_external_common
+ 4ca: f000 6d02 li a1,2
+ 4ca: R_MIPS16_HI16 small_external_common
+ 4ce: f400 35a0 sll a1,16
+ 4d2: f5b4 9d85 lw a0,-23131\(a1\)
+ 4d2: R_MIPS16_LO16 small_external_common
+ 4d6: f000 6d02 li a1,2
+ 4d6: R_MIPS16_HI16 \.bss
+ 4da: f400 35a0 sll a1,16
+ 4de: f5b4 9d85 lw a0,-23131\(a1\)
+ 4de: R_MIPS16_LO16 \.bss
+ 4e2: f000 6d02 li a1,2
+ 4e2: R_MIPS16_HI16 \.sbss
+ 4e6: f400 35a0 sll a1,16
+ 4ea: f5b4 9d85 lw a0,-23131\(a1\)
+ 4ea: R_MIPS16_LO16 \.sbss
+ 4ee: 6500 nop
diff -up --recursive --new-file binutils-2.15.94-20050214.macro/gas/testsuite/gas/mips/mips16-hilo.s binutils-2.15.94-20050214/gas/testsuite/gas/mips/mips16-hilo.s
--- binutils-2.15.94-20050214.macro/gas/testsuite/gas/mips/mips16-hilo.s 1970-01-01 00:00:00.000000000 +0000
+++ binutils-2.15.94-20050214/gas/testsuite/gas/mips/mips16-hilo.s 2005-02-10 16:26:17.000000000 +0000
@@ -0,0 +1,346 @@
+# Source file used to test li/addi on MIPS16
+
+ .set mips16
+
+ .data
+data_label:
+ .word 0
+data_label2:
+ .word 0
+
+ .extern big_external_data_label,1000
+ .extern small_external_data_label,1
+ .comm big_external_common,1000
+ .comm small_external_common,1
+ .lcomm big_local_common,1000
+ .lcomm small_local_common,1
+
+ .text
+stuff:
+ li $4,%hi(0)
+ sll $4,16
+ addiu $4,%lo(0)
+ li $4,%hi(data_label)
+ sll $4,16
+ addiu $4,%lo(data_label)
+ li $4,%hi(data_label2)
+ sll $4,16
+ addiu $4,%lo(data_label2)
+ li $4,%hi(big_external_data_label)
+ sll $4,16
+ addiu $4,%lo(big_external_data_label)
+ li $4,%hi(small_external_data_label)
+ sll $4,16
+ addiu $4,%lo(small_external_data_label)
+ li $4,%hi(big_external_common)
+ sll $4,16
+ addiu $4,%lo(big_external_common)
+ li $4,%hi(small_external_common)
+ sll $4,16
+ addiu $4,%lo(small_external_common)
+ li $4,%hi(big_local_common)
+ sll $4,16
+ addiu $4,%lo(big_local_common)
+ li $4,%hi(small_local_common)
+ sll $4,16
+ addiu $4,%lo(small_local_common)
+ li $4,%hi(1)
+ sll $4,16
+ addiu $4,%lo(1)
+ li $4,%hi(data_label+1)
+ sll $4,16
+ addiu $4,%lo(data_label+1)
+ li $4,%hi(data_label2+1)
+ sll $4,16
+ addiu $4,%lo(data_label2+1)
+ li $4,%hi(big_external_data_label+1)
+ sll $4,16
+ addiu $4,%lo(big_external_data_label+1)
+ li $4,%hi(small_external_data_label+1)
+ sll $4,16
+ addiu $4,%lo(small_external_data_label+1)
+ li $4,%hi(big_external_common+1)
+ sll $4,16
+ addiu $4,%lo(big_external_common+1)
+ li $4,%hi(small_external_common+1)
+ sll $4,16
+ addiu $4,%lo(small_external_common+1)
+ li $4,%hi(big_local_common+1)
+ sll $4,16
+ addiu $4,%lo(big_local_common+1)
+ li $4,%hi(small_local_common+1)
+ sll $4,16
+ addiu $4,%lo(small_local_common+1)
+ li $4,%hi(0x8000)
+ sll $4,16
+ addiu $4,%lo(0x8000)
+ li $4,%hi(data_label+0x8000)
+ sll $4,16
+ addiu $4,%lo(data_label+0x8000)
+ li $4,%hi(data_label2+0x8000)
+ sll $4,16
+ addiu $4,%lo(data_label2+0x8000)
+ li $4,%hi(big_external_data_label+0x8000)
+ sll $4,16
+ addiu $4,%lo(big_external_data_label+0x8000)
+ li $4,%hi(small_external_data_label+0x8000)
+ sll $4,16
+ addiu $4,%lo(small_external_data_label+0x8000)
+ li $4,%hi(big_external_common+0x8000)
+ sll $4,16
+ addiu $4,%lo(big_external_common+0x8000)
+ li $4,%hi(small_external_common+0x8000)
+ sll $4,16
+ addiu $4,%lo(small_external_common+0x8000)
+ li $4,%hi(big_local_common+0x8000)
+ sll $4,16
+ addiu $4,%lo(big_local_common+0x8000)
+ li $4,%hi(small_local_common+0x8000)
+ sll $4,16
+ addiu $4,%lo(small_local_common+0x8000)
+ li $4,%hi(-0x8000)
+ sll $4,16
+ addiu $4,%lo(-0x8000)
+ li $4,%hi(data_label-0x8000)
+ sll $4,16
+ addiu $4,%lo(data_label-0x8000)
+ li $4,%hi(data_label2-0x8000)
+ sll $4,16
+ addiu $4,%lo(data_label2-0x8000)
+ li $4,%hi(big_external_data_label-0x8000)
+ sll $4,16
+ addiu $4,%lo(big_external_data_label-0x8000)
+ li $4,%hi(small_external_data_label-0x8000)
+ sll $4,16
+ addiu $4,%lo(small_external_data_label-0x8000)
+ li $4,%hi(big_external_common-0x8000)
+ sll $4,16
+ addiu $4,%lo(big_external_common-0x8000)
+ li $4,%hi(small_external_common-0x8000)
+ sll $4,16
+ addiu $4,%lo(small_external_common-0x8000)
+ li $4,%hi(big_local_common-0x8000)
+ sll $4,16
+ addiu $4,%lo(big_local_common-0x8000)
+ li $4,%hi(small_local_common-0x8000)
+ sll $4,16
+ addiu $4,%lo(small_local_common-0x8000)
+ li $4,%hi(0x10000)
+ sll $4,16
+ addiu $4,%lo(0x10000)
+ li $4,%hi(data_label+0x10000)
+ sll $4,16
+ addiu $4,%lo(data_label+0x10000)
+ li $4,%hi(data_label2+0x10000)
+ sll $4,16
+ addiu $4,%lo(data_label2+0x10000)
+ li $4,%hi(big_external_data_label+0x10000)
+ sll $4,16
+ addiu $4,%lo(big_external_data_label+0x10000)
+ li $4,%hi(small_external_data_label+0x10000)
+ sll $4,16
+ addiu $4,%lo(small_external_data_label+0x10000)
+ li $4,%hi(big_external_common+0x10000)
+ sll $4,16
+ addiu $4,%lo(big_external_common+0x10000)
+ li $4,%hi(small_external_common+0x10000)
+ sll $4,16
+ addiu $4,%lo(small_external_common+0x10000)
+ li $4,%hi(big_local_common+0x10000)
+ sll $4,16
+ addiu $4,%lo(big_local_common+0x10000)
+ li $4,%hi(small_local_common+0x10000)
+ sll $4,16
+ addiu $4,%lo(small_local_common+0x10000)
+ li $4,%hi(0x1a5a5)
+ sll $4,16
+ addiu $4,%lo(0x1a5a5)
+ li $4,%hi(data_label+0x1a5a5)
+ sll $4,16
+ addiu $4,%lo(data_label+0x1a5a5)
+ li $4,%hi(data_label2+0x1a5a5)
+ sll $4,16
+ addiu $4,%lo(data_label2+0x1a5a5)
+ li $4,%hi(big_external_data_label+0x1a5a5)
+ sll $4,16
+ addiu $4,%lo(big_external_data_label+0x1a5a5)
+ li $4,%hi(small_external_data_label+0x1a5a5)
+ sll $4,16
+ addiu $4,%lo(small_external_data_label+0x1a5a5)
+ li $4,%hi(big_external_common+0x1a5a5)
+ sll $4,16
+ addiu $4,%lo(big_external_common+0x1a5a5)
+ li $4,%hi(small_external_common+0x1a5a5)
+ sll $4,16
+ addiu $4,%lo(small_external_common+0x1a5a5)
+ li $4,%hi(big_local_common+0x1a5a5)
+ sll $4,16
+ addiu $4,%lo(big_local_common+0x1a5a5)
+ li $4,%hi(small_local_common+0x1a5a5)
+ sll $4,16
+ addiu $4,%lo(small_local_common+0x1a5a5)
+ li $5,%hi(0)
+ sll $5,16
+ lw $4,%hi(0)($5)
+ li $5,%hi(data_label)
+ sll $5,16
+ lw $4,%hi(data_label)($5)
+ li $5,%hi(data_label2)
+ sll $5,16
+ lw $4,%hi(data_label2)($5)
+ li $5,%hi(big_external_data_label)
+ sll $5,16
+ lw $4,%lo(big_external_data_label)($5)
+ li $5,%hi(small_external_data_label)
+ sll $5,16
+ lw $4,%lo(small_external_data_label)($5)
+ li $5,%hi(big_external_common)
+ sll $5,16
+ lw $4,%lo(big_external_common)($5)
+ li $5,%hi(small_external_common)
+ sll $5,16
+ lw $4,%lo(small_external_common)($5)
+ li $5,%hi(big_local_common)
+ sll $5,16
+ lw $4,%lo(big_local_common)($5)
+ li $5,%hi(small_local_common)
+ sll $5,16
+ lw $4,%lo(small_local_common)($5)
+ li $5,%hi(1)
+ sll $5,16
+ lw $4,%lo(1)($5)
+ li $5,%hi(data_label+1)
+ sll $5,16
+ lw $4,%lo(data_label+1)($5)
+ li $5,%hi(data_label2+1)
+ sll $5,16
+ lw $4,%lo(data_label2+1)($5)
+ li $5,%hi(big_external_data_label+1)
+ sll $5,16
+ lw $4,%lo(big_external_data_label+1)($5)
+ li $5,%hi(small_external_data_label+1)
+ sll $5,16
+ lw $4,%lo(small_external_data_label+1)($5)
+ li $5,%hi(big_external_common+1)
+ sll $5,16
+ lw $4,%lo(big_external_common+1)($5)
+ li $5,%hi(small_external_common+1)
+ sll $5,16
+ lw $4,%lo(small_external_common+1)($5)
+ li $5,%hi(big_local_common+1)
+ sll $5,16
+ lw $4,%lo(big_local_common+1)($5)
+ li $5,%hi(small_local_common+1)
+ sll $5,16
+ lw $4,%lo(small_local_common+1)($5)
+ li $5,%hi(0x8000)
+ sll $5,16
+ lw $4,%lo(0x8000)($5)
+ li $5,%hi(data_label+0x8000)
+ sll $5,16
+ lw $4,%lo(data_label+0x8000)($5)
+ li $5,%hi(data_label2+0x8000)
+ sll $5,16
+ lw $4,%lo(data_label2+0x8000)($5)
+ li $5,%hi(big_external_data_label+0x8000)
+ sll $5,16
+ lw $4,%lo(big_external_data_label+0x8000)($5)
+ li $5,%hi(small_external_data_label+0x8000)
+ sll $5,16
+ lw $4,%lo(small_external_data_label+0x8000)($5)
+ li $5,%hi(big_external_common+0x8000)
+ sll $5,16
+ lw $4,%lo(big_external_common+0x8000)($5)
+ li $5,%hi(small_external_common+0x8000)
+ sll $5,16
+ lw $4,%lo(small_external_common+0x8000)($5)
+ li $5,%hi(big_local_common+0x8000)
+ sll $5,16
+ lw $4,%lo(big_local_common+0x8000)($5)
+ li $5,%hi(small_local_common+0x8000)
+ sll $5,16
+ lw $4,%lo(small_local_common+0x8000)($5)
+ li $5,%hi(-0x8000)
+ sll $5,16
+ lw $4,%lo(-0x8000)($5)
+ li $5,%hi(data_label-0x8000)
+ sll $5,16
+ lw $4,%lo(data_label-0x8000)($5)
+ li $5,%hi(data_label2-0x8000)
+ sll $5,16
+ lw $4,%lo(data_label2-0x8000)($5)
+ li $5,%hi(big_external_data_label-0x8000)
+ sll $5,16
+ lw $4,%lo(big_external_data_label-0x8000)($5)
+ li $5,%hi(small_external_data_label-0x8000)
+ sll $5,16
+ lw $4,%lo(small_external_data_label-0x8000)($5)
+ li $5,%hi(big_external_common-0x8000)
+ sll $5,16
+ lw $4,%lo(big_external_common-0x8000)($5)
+ li $5,%hi(small_external_common-0x8000)
+ sll $5,16
+ lw $4,%lo(small_external_common-0x8000)($5)
+ li $5,%hi(big_local_common-0x8000)
+ sll $5,16
+ lw $4,%lo(big_local_common-0x8000)($5)
+ li $5,%hi(small_local_common-0x8000)
+ sll $5,16
+ lw $4,%lo(small_local_common-0x8000)($5)
+ li $5,%hi(0x10000)
+ sll $5,16
+ lw $4,%lo(0x10000)($5)
+ li $5,%hi(data_label+0x10000)
+ sll $5,16
+ lw $4,%lo(data_label+0x10000)($5)
+ li $5,%hi(data_label2+0x10000)
+ sll $5,16
+ lw $4,%lo(data_label2+0x10000)($5)
+ li $5,%hi(big_external_data_label+0x10000)
+ sll $5,16
+ lw $4,%lo(big_external_data_label+0x10000)($5)
+ li $5,%hi(small_external_data_label+0x10000)
+ sll $5,16
+ lw $4,%lo(small_external_data_label+0x10000)($5)
+ li $5,%hi(big_external_common+0x10000)
+ sll $5,16
+ lw $4,%lo(big_external_common+0x10000)($5)
+ li $5,%hi(small_external_common+0x10000)
+ sll $5,16
+ lw $4,%lo(small_external_common+0x10000)($5)
+ li $5,%hi(big_local_common+0x10000)
+ sll $5,16
+ lw $4,%lo(big_local_common+0x10000)($5)
+ li $5,%hi(small_local_common+0x10000)
+ sll $5,16
+ lw $4,%lo(small_local_common+0x10000)($5)
+ li $5,%hi(0x1a5a5)
+ sll $5,16
+ lw $4,%lo(0x1a5a5)($5)
+ li $5,%hi(data_label+0x1a5a5)
+ sll $5,16
+ lw $4,%lo(data_label+0x1a5a5)($5)
+ li $5,%hi(data_label2+0x1a5a5)
+ sll $5,16
+ lw $4,%lo(data_label2+0x1a5a5)($5)
+ li $5,%hi(big_external_data_label+0x1a5a5)
+ sll $5,16
+ lw $4,%lo(big_external_data_label+0x1a5a5)($5)
+ li $5,%hi(small_external_data_label+0x1a5a5)
+ sll $5,16
+ lw $4,%lo(small_external_data_label+0x1a5a5)($5)
+ li $5,%hi(big_external_common+0x1a5a5)
+ sll $5,16
+ lw $4,%lo(big_external_common+0x1a5a5)($5)
+ li $5,%hi(small_external_common+0x1a5a5)
+ sll $5,16
+ lw $4,%lo(small_external_common+0x1a5a5)($5)
+ li $5,%hi(big_local_common+0x1a5a5)
+ sll $5,16
+ lw $4,%lo(big_local_common+0x1a5a5)($5)
+ li $5,%hi(small_local_common+0x1a5a5)
+ sll $5,16
+ lw $4,%lo(small_local_common+0x1a5a5)($5)
+
+# align section end to 16-byte boundary for easier testing on multiple targets
+ .p2align 4
diff -up --recursive --new-file binutils-2.15.94-20050214.macro/include/elf/mips.h binutils-2.15.94-20050214/include/elf/mips.h
--- binutils-2.15.94-20050214.macro/include/elf/mips.h 2005-02-14 11:40:03.000000000 +0000
+++ binutils-2.15.94-20050214/include/elf/mips.h 2005-02-14 11:44:27.000000000 +0000
@@ -74,8 +74,14 @@ START_RELOC_NUMBERS (elf_mips_reloc_type
RELOC_NUMBER (R_MIPS_JALR, 37)
FAKE_RELOC (R_MIPS_max, 38)
/* These relocs are used for the mips16. */
+ FAKE_RELOC (R_MIPS16_min, 100)
RELOC_NUMBER (R_MIPS16_26, 100)
RELOC_NUMBER (R_MIPS16_GPREL, 101)
+ RELOC_NUMBER (R_MIPS16_GOT16, 102)
+ RELOC_NUMBER (R_MIPS16_CALL16, 103)
+ RELOC_NUMBER (R_MIPS16_HI16, 104)
+ RELOC_NUMBER (R_MIPS16_LO16, 105)
+ FAKE_RELOC (R_MIPS16_max, 106)
/* This was a GNU extension used by embedded-PIC. It was co-opted by
mips-linux for exception-handling data. It is no longer used, but
should continue to be supported by the linker for backward
diff -up --recursive --new-file binutils-2.15.94-20050214.macro/ld/testsuite/ld-mips-elf/mips-elf.exp binutils-2.15.94-20050214/ld/testsuite/ld-mips-elf/mips-elf.exp
--- binutils-2.15.94-20050214.macro/ld/testsuite/ld-mips-elf/mips-elf.exp 2005-02-14 11:40:08.000000000 +0000
+++ binutils-2.15.94-20050214/ld/testsuite/ld-mips-elf/mips-elf.exp 2005-02-14 11:44:27.000000000 +0000
@@ -94,3 +94,8 @@ run_dump_test "jaloverflow-2"
if {$has_newabi} {
run_dump_test "jalbal"
}
+
+run_dump_test "mips16-hilo"
+if {$has_newabi} {
+ run_dump_test "mips16-hilo-n32"
+}
diff -up --recursive --new-file binutils-2.15.94-20050214.macro/ld/testsuite/ld-mips-elf/mips16-hilo-n32.d binutils-2.15.94-20050214/ld/testsuite/ld-mips-elf/mips16-hilo-n32.d
--- binutils-2.15.94-20050214.macro/ld/testsuite/ld-mips-elf/mips16-hilo-n32.d 1970-01-01 00:00:00.000000000 +0000
+++ binutils-2.15.94-20050214/ld/testsuite/ld-mips-elf/mips16-hilo-n32.d 2005-02-12 05:52:57.000000000 +0000
@@ -0,0 +1,338 @@
+#name: R_MIPS16_HI16 and R_MIPS16_LO16 relocs n32
+#source: ../../../gas/testsuite/gas/mips/mips16-hilo.s
+#source: mips16-hilo.s
+#as: -march=mips64 -mabi=n32 -EB
+#objdump: -mmips:16 --prefix-addresses -tdr --show-raw-insn
+#ld: -Tmips16-hilo.ld -e 0x500000 -N -melf32btsmipn32
+
+.*: file format elf.*mips.*
+
+#...
+
+Disassembly of section .text:
+0+500000 <[^>]*> 6c00 li a0,0
+0+500002 <[^>]*> f400 3480 sll a0,16
+0+500006 <[^>]*> 4c00 addiu a0,0
+0+500008 <[^>]*> f060 6c05 li a0,101
+0+50000c <[^>]*> f400 3480 sll a0,16
+0+500010 <[^>]*> f328 4c00 addiu a0,17184
+0+500014 <[^>]*> f060 6c05 li a0,101
+0+500018 <[^>]*> f400 3480 sll a0,16
+0+50001c <[^>]*> f328 4c04 addiu a0,17188
+0+500020 <[^>]*> f060 6c05 li a0,101
+0+500024 <[^>]*> f400 3480 sll a0,16
+0+500028 <[^>]*> f328 4c10 addiu a0,17200
+0+50002c <[^>]*> f060 6c05 li a0,101
+0+500030 <[^>]*> f400 3480 sll a0,16
+0+500034 <[^>]*> f728 4c00 addiu a0,18208
+0+500038 <[^>]*> f060 6c16 li a0,118
+0+50003c <[^>]*> f400 3480 sll a0,16
+0+500040 <[^>]*> f02b 4c00 addiu a0,22560
+0+500044 <[^>]*> f060 6c16 li a0,118
+0+500048 <[^>]*> f400 3480 sll a0,16
+0+50004c <[^>]*> f40b 4c09 addiu a0,23561
+0+500050 <[^>]*> f060 6c16 li a0,118
+0+500054 <[^>]*> f400 3480 sll a0,16
+0+500058 <[^>]*> f42a 4c10 addiu a0,21552
+0+50005c <[^>]*> f060 6c16 li a0,118
+0+500060 <[^>]*> f400 3480 sll a0,16
+0+500064 <[^>]*> f40b 4c08 addiu a0,23560
+0+500068 <[^>]*> 6c00 li a0,0
+0+50006a <[^>]*> f400 3480 sll a0,16
+0+50006e <[^>]*> 4c01 addiu a0,1
+0+500070 <[^>]*> f060 6c05 li a0,101
+0+500074 <[^>]*> f400 3480 sll a0,16
+0+500078 <[^>]*> f328 4c01 addiu a0,17185
+0+50007c <[^>]*> f060 6c05 li a0,101
+0+500080 <[^>]*> f400 3480 sll a0,16
+0+500084 <[^>]*> f328 4c05 addiu a0,17189
+0+500088 <[^>]*> f060 6c05 li a0,101
+0+50008c <[^>]*> f400 3480 sll a0,16
+0+500090 <[^>]*> f328 4c11 addiu a0,17201
+0+500094 <[^>]*> f060 6c05 li a0,101
+0+500098 <[^>]*> f400 3480 sll a0,16
+0+50009c <[^>]*> f728 4c01 addiu a0,18209
+0+5000a0 <[^>]*> f060 6c16 li a0,118
+0+5000a4 <[^>]*> f400 3480 sll a0,16
+0+5000a8 <[^>]*> f02b 4c01 addiu a0,22561
+0+5000ac <[^>]*> f060 6c16 li a0,118
+0+5000b0 <[^>]*> f400 3480 sll a0,16
+0+5000b4 <[^>]*> f40b 4c0a addiu a0,23562
+0+5000b8 <[^>]*> f060 6c16 li a0,118
+0+5000bc <[^>]*> f400 3480 sll a0,16
+0+5000c0 <[^>]*> f42a 4c11 addiu a0,21553
+0+5000c4 <[^>]*> f060 6c16 li a0,118
+0+5000c8 <[^>]*> f400 3480 sll a0,16
+0+5000cc <[^>]*> f40b 4c09 addiu a0,23561
+0+5000d0 <[^>]*> 6c01 li a0,1
+0+5000d2 <[^>]*> f400 3480 sll a0,16
+0+5000d6 <[^>]*> f010 4c00 addiu a0,-32768
+0+5000da <[^>]*> f060 6c06 li a0,102
+0+5000de <[^>]*> f400 3480 sll a0,16
+0+5000e2 <[^>]*> f338 4c00 addiu a0,-15584
+0+5000e6 <[^>]*> f060 6c06 li a0,102
+0+5000ea <[^>]*> f400 3480 sll a0,16
+0+5000ee <[^>]*> f338 4c04 addiu a0,-15580
+0+5000f2 <[^>]*> f060 6c06 li a0,102
+0+5000f6 <[^>]*> f400 3480 sll a0,16
+0+5000fa <[^>]*> f338 4c10 addiu a0,-15568
+0+5000fe <[^>]*> f060 6c06 li a0,102
+0+500102 <[^>]*> f400 3480 sll a0,16
+0+500106 <[^>]*> f738 4c00 addiu a0,-14560
+0+50010a <[^>]*> f060 6c17 li a0,119
+0+50010e <[^>]*> f400 3480 sll a0,16
+0+500112 <[^>]*> f03b 4c00 addiu a0,-10208
+0+500116 <[^>]*> f060 6c17 li a0,119
+0+50011a <[^>]*> f400 3480 sll a0,16
+0+50011e <[^>]*> f41b 4c09 addiu a0,-9207
+0+500122 <[^>]*> f060 6c17 li a0,119
+0+500126 <[^>]*> f400 3480 sll a0,16
+0+50012a <[^>]*> f43a 4c10 addiu a0,-11216
+0+50012e <[^>]*> f060 6c17 li a0,119
+0+500132 <[^>]*> f400 3480 sll a0,16
+0+500136 <[^>]*> f41b 4c08 addiu a0,-9208
+0+50013a <[^>]*> 6c00 li a0,0
+0+50013c <[^>]*> f400 3480 sll a0,16
+0+500140 <[^>]*> f010 4c00 addiu a0,-32768
+0+500144 <[^>]*> f060 6c05 li a0,101
+0+500148 <[^>]*> f400 3480 sll a0,16
+0+50014c <[^>]*> f338 4c00 addiu a0,-15584
+0+500150 <[^>]*> f060 6c05 li a0,101
+0+500154 <[^>]*> f400 3480 sll a0,16
+0+500158 <[^>]*> f338 4c04 addiu a0,-15580
+0+50015c <[^>]*> f060 6c05 li a0,101
+0+500160 <[^>]*> f400 3480 sll a0,16
+0+500164 <[^>]*> f338 4c10 addiu a0,-15568
+0+500168 <[^>]*> f060 6c05 li a0,101
+0+50016c <[^>]*> f400 3480 sll a0,16
+0+500170 <[^>]*> f738 4c00 addiu a0,-14560
+0+500174 <[^>]*> f060 6c16 li a0,118
+0+500178 <[^>]*> f400 3480 sll a0,16
+0+50017c <[^>]*> f03b 4c00 addiu a0,-10208
+0+500180 <[^>]*> f060 6c16 li a0,118
+0+500184 <[^>]*> f400 3480 sll a0,16
+0+500188 <[^>]*> f41b 4c09 addiu a0,-9207
+0+50018c <[^>]*> f060 6c16 li a0,118
+0+500190 <[^>]*> f400 3480 sll a0,16
+0+500194 <[^>]*> f43a 4c10 addiu a0,-11216
+0+500198 <[^>]*> f060 6c16 li a0,118
+0+50019c <[^>]*> f400 3480 sll a0,16
+0+5001a0 <[^>]*> f41b 4c08 addiu a0,-9208
+0+5001a4 <[^>]*> 6c01 li a0,1
+0+5001a6 <[^>]*> f400 3480 sll a0,16
+0+5001aa <[^>]*> 4c00 addiu a0,0
+0+5001ac <[^>]*> f060 6c06 li a0,102
+0+5001b0 <[^>]*> f400 3480 sll a0,16
+0+5001b4 <[^>]*> f328 4c00 addiu a0,17184
+0+5001b8 <[^>]*> f060 6c06 li a0,102
+0+5001bc <[^>]*> f400 3480 sll a0,16
+0+5001c0 <[^>]*> f328 4c04 addiu a0,17188
+0+5001c4 <[^>]*> f060 6c06 li a0,102
+0+5001c8 <[^>]*> f400 3480 sll a0,16
+0+5001cc <[^>]*> f328 4c10 addiu a0,17200
+0+5001d0 <[^>]*> f060 6c06 li a0,102
+0+5001d4 <[^>]*> f400 3480 sll a0,16
+0+5001d8 <[^>]*> f728 4c00 addiu a0,18208
+0+5001dc <[^>]*> f060 6c17 li a0,119
+0+5001e0 <[^>]*> f400 3480 sll a0,16
+0+5001e4 <[^>]*> f02b 4c00 addiu a0,22560
+0+5001e8 <[^>]*> f060 6c17 li a0,119
+0+5001ec <[^>]*> f400 3480 sll a0,16
+0+5001f0 <[^>]*> f40b 4c09 addiu a0,23561
+0+5001f4 <[^>]*> f060 6c17 li a0,119
+0+5001f8 <[^>]*> f400 3480 sll a0,16
+0+5001fc <[^>]*> f42a 4c10 addiu a0,21552
+0+500200 <[^>]*> f060 6c17 li a0,119
+0+500204 <[^>]*> f400 3480 sll a0,16
+0+500208 <[^>]*> f40b 4c08 addiu a0,23560
+0+50020c <[^>]*> 6c02 li a0,2
+0+50020e <[^>]*> f400 3480 sll a0,16
+0+500212 <[^>]*> f5b4 4c05 addiu a0,-23131
+0+500216 <[^>]*> f060 6c07 li a0,103
+0+50021a <[^>]*> f400 3480 sll a0,16
+0+50021e <[^>]*> f0dd 4c05 addiu a0,-5947
+0+500222 <[^>]*> f060 6c07 li a0,103
+0+500226 <[^>]*> f400 3480 sll a0,16
+0+50022a <[^>]*> f0dd 4c09 addiu a0,-5943
+0+50022e <[^>]*> f060 6c07 li a0,103
+0+500232 <[^>]*> f400 3480 sll a0,16
+0+500236 <[^>]*> f0dd 4c15 addiu a0,-5931
+0+50023a <[^>]*> f060 6c07 li a0,103
+0+50023e <[^>]*> f400 3480 sll a0,16
+0+500242 <[^>]*> f4dd 4c05 addiu a0,-4923
+0+500246 <[^>]*> f060 6c18 li a0,120
+0+50024a <[^>]*> f400 3480 sll a0,16
+0+50024e <[^>]*> f5df 4c05 addiu a0,-571
+0+500252 <[^>]*> f060 6c18 li a0,120
+0+500256 <[^>]*> f400 3480 sll a0,16
+0+50025a <[^>]*> f1a0 4c0e addiu a0,430
+0+50025e <[^>]*> f060 6c18 li a0,120
+0+500262 <[^>]*> f400 3480 sll a0,16
+0+500266 <[^>]*> f1df 4c15 addiu a0,-1579
+0+50026a <[^>]*> f060 6c18 li a0,120
+0+50026e <[^>]*> f400 3480 sll a0,16
+0+500272 <[^>]*> f1a0 4c0d addiu a0,429
+0+500276 <[^>]*> 6d00 li a1,0
+0+500278 <[^>]*> f400 35a0 sll a1,16
+0+50027c <[^>]*> 9d80 lw a0,0\(a1\)
+0+50027e <[^>]*> f060 6d05 li a1,101
+0+500282 <[^>]*> f400 35a0 sll a1,16
+0+500286 <[^>]*> f060 9d85 lw a0,101\(a1\)
+0+50028a <[^>]*> f060 6d05 li a1,101
+0+50028e <[^>]*> f400 35a0 sll a1,16
+0+500292 <[^>]*> f060 9d85 lw a0,101\(a1\)
+0+500296 <[^>]*> f060 6d05 li a1,101
+0+50029a <[^>]*> f400 35a0 sll a1,16
+0+50029e <[^>]*> f328 9d90 lw a0,17200\(a1\)
+0+5002a2 <[^>]*> f060 6d05 li a1,101
+0+5002a6 <[^>]*> f400 35a0 sll a1,16
+0+5002aa <[^>]*> f728 9d80 lw a0,18208\(a1\)
+0+5002ae <[^>]*> f060 6d16 li a1,118
+0+5002b2 <[^>]*> f400 35a0 sll a1,16
+0+5002b6 <[^>]*> f02b 9d80 lw a0,22560\(a1\)
+0+5002ba <[^>]*> f060 6d16 li a1,118
+0+5002be <[^>]*> f400 35a0 sll a1,16
+0+5002c2 <[^>]*> f40b 9d89 lw a0,23561\(a1\)
+0+5002c6 <[^>]*> f060 6d16 li a1,118
+0+5002ca <[^>]*> f400 35a0 sll a1,16
+0+5002ce <[^>]*> f42a 9d90 lw a0,21552\(a1\)
+0+5002d2 <[^>]*> f060 6d16 li a1,118
+0+5002d6 <[^>]*> f400 35a0 sll a1,16
+0+5002da <[^>]*> f40b 9d88 lw a0,23560\(a1\)
+0+5002de <[^>]*> 6d00 li a1,0
+0+5002e0 <[^>]*> f400 35a0 sll a1,16
+0+5002e4 <[^>]*> f000 9d81 lw a0,1\(a1\)
+0+5002e8 <[^>]*> f060 6d05 li a1,101
+0+5002ec <[^>]*> f400 35a0 sll a1,16
+0+5002f0 <[^>]*> f328 9d81 lw a0,17185\(a1\)
+0+5002f4 <[^>]*> f060 6d05 li a1,101
+0+5002f8 <[^>]*> f400 35a0 sll a1,16
+0+5002fc <[^>]*> f328 9d85 lw a0,17189\(a1\)
+0+500300 <[^>]*> f060 6d05 li a1,101
+0+500304 <[^>]*> f400 35a0 sll a1,16
+0+500308 <[^>]*> f328 9d91 lw a0,17201\(a1\)
+0+50030c <[^>]*> f060 6d05 li a1,101
+0+500310 <[^>]*> f400 35a0 sll a1,16
+0+500314 <[^>]*> f728 9d81 lw a0,18209\(a1\)
+0+500318 <[^>]*> f060 6d16 li a1,118
+0+50031c <[^>]*> f400 35a0 sll a1,16
+0+500320 <[^>]*> f02b 9d81 lw a0,22561\(a1\)
+0+500324 <[^>]*> f060 6d16 li a1,118
+0+500328 <[^>]*> f400 35a0 sll a1,16
+0+50032c <[^>]*> f40b 9d8a lw a0,23562\(a1\)
+0+500330 <[^>]*> f060 6d16 li a1,118
+0+500334 <[^>]*> f400 35a0 sll a1,16
+0+500338 <[^>]*> f42a 9d91 lw a0,21553\(a1\)
+0+50033c <[^>]*> f060 6d16 li a1,118
+0+500340 <[^>]*> f400 35a0 sll a1,16
+0+500344 <[^>]*> f40b 9d89 lw a0,23561\(a1\)
+0+500348 <[^>]*> 6d01 li a1,1
+0+50034a <[^>]*> f400 35a0 sll a1,16
+0+50034e <[^>]*> f010 9d80 lw a0,-32768\(a1\)
+0+500352 <[^>]*> f060 6d06 li a1,102
+0+500356 <[^>]*> f400 35a0 sll a1,16
+0+50035a <[^>]*> f338 9d80 lw a0,-15584\(a1\)
+0+50035e <[^>]*> f060 6d06 li a1,102
+0+500362 <[^>]*> f400 35a0 sll a1,16
+0+500366 <[^>]*> f338 9d84 lw a0,-15580\(a1\)
+0+50036a <[^>]*> f060 6d06 li a1,102
+0+50036e <[^>]*> f400 35a0 sll a1,16
+0+500372 <[^>]*> f338 9d90 lw a0,-15568\(a1\)
+0+500376 <[^>]*> f060 6d06 li a1,102
+0+50037a <[^>]*> f400 35a0 sll a1,16
+0+50037e <[^>]*> f738 9d80 lw a0,-14560\(a1\)
+0+500382 <[^>]*> f060 6d17 li a1,119
+0+500386 <[^>]*> f400 35a0 sll a1,16
+0+50038a <[^>]*> f03b 9d80 lw a0,-10208\(a1\)
+0+50038e <[^>]*> f060 6d17 li a1,119
+0+500392 <[^>]*> f400 35a0 sll a1,16
+0+500396 <[^>]*> f41b 9d89 lw a0,-9207\(a1\)
+0+50039a <[^>]*> f060 6d17 li a1,119
+0+50039e <[^>]*> f400 35a0 sll a1,16
+0+5003a2 <[^>]*> f43a 9d90 lw a0,-11216\(a1\)
+0+5003a6 <[^>]*> f060 6d17 li a1,119
+0+5003aa <[^>]*> f400 35a0 sll a1,16
+0+5003ae <[^>]*> f41b 9d88 lw a0,-9208\(a1\)
+0+5003b2 <[^>]*> 6d00 li a1,0
+0+5003b4 <[^>]*> f400 35a0 sll a1,16
+0+5003b8 <[^>]*> f010 9d80 lw a0,-32768\(a1\)
+0+5003bc <[^>]*> f060 6d05 li a1,101
+0+5003c0 <[^>]*> f400 35a0 sll a1,16
+0+5003c4 <[^>]*> f338 9d80 lw a0,-15584\(a1\)
+0+5003c8 <[^>]*> f060 6d05 li a1,101
+0+5003cc <[^>]*> f400 35a0 sll a1,16
+0+5003d0 <[^>]*> f338 9d84 lw a0,-15580\(a1\)
+0+5003d4 <[^>]*> f060 6d05 li a1,101
+0+5003d8 <[^>]*> f400 35a0 sll a1,16
+0+5003dc <[^>]*> f338 9d90 lw a0,-15568\(a1\)
+0+5003e0 <[^>]*> f060 6d05 li a1,101
+0+5003e4 <[^>]*> f400 35a0 sll a1,16
+0+5003e8 <[^>]*> f738 9d80 lw a0,-14560\(a1\)
+0+5003ec <[^>]*> f060 6d16 li a1,118
+0+5003f0 <[^>]*> f400 35a0 sll a1,16
+0+5003f4 <[^>]*> f03b 9d80 lw a0,-10208\(a1\)
+0+5003f8 <[^>]*> f060 6d16 li a1,118
+0+5003fc <[^>]*> f400 35a0 sll a1,16
+0+500400 <[^>]*> f41b 9d89 lw a0,-9207\(a1\)
+0+500404 <[^>]*> f060 6d16 li a1,118
+0+500408 <[^>]*> f400 35a0 sll a1,16
+0+50040c <[^>]*> f43a 9d90 lw a0,-11216\(a1\)
+0+500410 <[^>]*> f060 6d16 li a1,118
+0+500414 <[^>]*> f400 35a0 sll a1,16
+0+500418 <[^>]*> f41b 9d88 lw a0,-9208\(a1\)
+0+50041c <[^>]*> 6d01 li a1,1
+0+50041e <[^>]*> f400 35a0 sll a1,16
+0+500422 <[^>]*> 9d80 lw a0,0\(a1\)
+0+500424 <[^>]*> f060 6d06 li a1,102
+0+500428 <[^>]*> f400 35a0 sll a1,16
+0+50042c <[^>]*> f328 9d80 lw a0,17184\(a1\)
+0+500430 <[^>]*> f060 6d06 li a1,102
+0+500434 <[^>]*> f400 35a0 sll a1,16
+0+500438 <[^>]*> f328 9d84 lw a0,17188\(a1\)
+0+50043c <[^>]*> f060 6d06 li a1,102
+0+500440 <[^>]*> f400 35a0 sll a1,16
+0+500444 <[^>]*> f328 9d90 lw a0,17200\(a1\)
+0+500448 <[^>]*> f060 6d06 li a1,102
+0+50044c <[^>]*> f400 35a0 sll a1,16
+0+500450 <[^>]*> f728 9d80 lw a0,18208\(a1\)
+0+500454 <[^>]*> f060 6d17 li a1,119
+0+500458 <[^>]*> f400 35a0 sll a1,16
+0+50045c <[^>]*> f02b 9d80 lw a0,22560\(a1\)
+0+500460 <[^>]*> f060 6d17 li a1,119
+0+500464 <[^>]*> f400 35a0 sll a1,16
+0+500468 <[^>]*> f40b 9d89 lw a0,23561\(a1\)
+0+50046c <[^>]*> f060 6d17 li a1,119
+0+500470 <[^>]*> f400 35a0 sll a1,16
+0+500474 <[^>]*> f42a 9d90 lw a0,21552\(a1\)
+0+500478 <[^>]*> f060 6d17 li a1,119
+0+50047c <[^>]*> f400 35a0 sll a1,16
+0+500480 <[^>]*> f40b 9d88 lw a0,23560\(a1\)
+0+500484 <[^>]*> 6d02 li a1,2
+0+500486 <[^>]*> f400 35a0 sll a1,16
+0+50048a <[^>]*> f5b4 9d85 lw a0,-23131\(a1\)
+0+50048e <[^>]*> f060 6d07 li a1,103
+0+500492 <[^>]*> f400 35a0 sll a1,16
+0+500496 <[^>]*> f0dd 9d85 lw a0,-5947\(a1\)
+0+50049a <[^>]*> f060 6d07 li a1,103
+0+50049e <[^>]*> f400 35a0 sll a1,16
+0+5004a2 <[^>]*> f0dd 9d89 lw a0,-5943\(a1\)
+0+5004a6 <[^>]*> f060 6d07 li a1,103
+0+5004aa <[^>]*> f400 35a0 sll a1,16
+0+5004ae <[^>]*> f0dd 9d95 lw a0,-5931\(a1\)
+0+5004b2 <[^>]*> f060 6d07 li a1,103
+0+5004b6 <[^>]*> f400 35a0 sll a1,16
+0+5004ba <[^>]*> f4dd 9d85 lw a0,-4923\(a1\)
+0+5004be <[^>]*> f060 6d18 li a1,120
+0+5004c2 <[^>]*> f400 35a0 sll a1,16
+0+5004c6 <[^>]*> f5df 9d85 lw a0,-571\(a1\)
+0+5004ca <[^>]*> f060 6d18 li a1,120
+0+5004ce <[^>]*> f400 35a0 sll a1,16
+0+5004d2 <[^>]*> f1a0 9d8e lw a0,430\(a1\)
+0+5004d6 <[^>]*> f060 6d18 li a1,120
+0+5004da <[^>]*> f400 35a0 sll a1,16
+0+5004de <[^>]*> f1df 9d95 lw a0,-1579\(a1\)
+0+5004e2 <[^>]*> f060 6d18 li a1,120
+0+5004e6 <[^>]*> f400 35a0 sll a1,16
+0+5004ea <[^>]*> f1a0 9d8d lw a0,429\(a1\)
+0+5004ee <[^>]*> 6500 nop
+#pass
diff -up --recursive --new-file binutils-2.15.94-20050214.macro/ld/testsuite/ld-mips-elf/mips16-hilo.d binutils-2.15.94-20050214/ld/testsuite/ld-mips-elf/mips16-hilo.d
--- binutils-2.15.94-20050214.macro/ld/testsuite/ld-mips-elf/mips16-hilo.d 1970-01-01 00:00:00.000000000 +0000
+++ binutils-2.15.94-20050214/ld/testsuite/ld-mips-elf/mips16-hilo.d 2005-02-12 05:53:28.000000000 +0000
@@ -0,0 +1,337 @@
+#name: R_MIPS16_HI16 and R_MIPS16_LO16 relocs
+#source: ../../../gas/testsuite/gas/mips/mips16-hilo.s
+#source: mips16-hilo.s
+#objdump: -mmips:16 --prefix-addresses -tdr --show-raw-insn
+#ld: -Tmips16-hilo.ld -e 0x500000 -N
+
+.*: file format elf.*mips.*
+
+#...
+
+Disassembly of section .text:
+0+500000 <[^>]*> 6c00 li a0,0
+0+500002 <[^>]*> f400 3480 sll a0,16
+0+500006 <[^>]*> 4c00 addiu a0,0
+0+500008 <[^>]*> f060 6c05 li a0,101
+0+50000c <[^>]*> f400 3480 sll a0,16
+0+500010 <[^>]*> f328 4c00 addiu a0,17184
+0+500014 <[^>]*> f060 6c05 li a0,101
+0+500018 <[^>]*> f400 3480 sll a0,16
+0+50001c <[^>]*> f328 4c04 addiu a0,17188
+0+500020 <[^>]*> f060 6c05 li a0,101
+0+500024 <[^>]*> f400 3480 sll a0,16
+0+500028 <[^>]*> f328 4c10 addiu a0,17200
+0+50002c <[^>]*> f060 6c05 li a0,101
+0+500030 <[^>]*> f400 3480 sll a0,16
+0+500034 <[^>]*> f728 4c00 addiu a0,18208
+0+500038 <[^>]*> f060 6c16 li a0,118
+0+50003c <[^>]*> f400 3480 sll a0,16
+0+500040 <[^>]*> f02b 4c00 addiu a0,22560
+0+500044 <[^>]*> f060 6c16 li a0,118
+0+500048 <[^>]*> f400 3480 sll a0,16
+0+50004c <[^>]*> f40b 4c09 addiu a0,23561
+0+500050 <[^>]*> f060 6c16 li a0,118
+0+500054 <[^>]*> f400 3480 sll a0,16
+0+500058 <[^>]*> f42a 4c10 addiu a0,21552
+0+50005c <[^>]*> f060 6c16 li a0,118
+0+500060 <[^>]*> f400 3480 sll a0,16
+0+500064 <[^>]*> f40b 4c08 addiu a0,23560
+0+500068 <[^>]*> 6c00 li a0,0
+0+50006a <[^>]*> f400 3480 sll a0,16
+0+50006e <[^>]*> 4c01 addiu a0,1
+0+500070 <[^>]*> f060 6c05 li a0,101
+0+500074 <[^>]*> f400 3480 sll a0,16
+0+500078 <[^>]*> f328 4c01 addiu a0,17185
+0+50007c <[^>]*> f060 6c05 li a0,101
+0+500080 <[^>]*> f400 3480 sll a0,16
+0+500084 <[^>]*> f328 4c05 addiu a0,17189
+0+500088 <[^>]*> f060 6c05 li a0,101
+0+50008c <[^>]*> f400 3480 sll a0,16
+0+500090 <[^>]*> f328 4c11 addiu a0,17201
+0+500094 <[^>]*> f060 6c05 li a0,101
+0+500098 <[^>]*> f400 3480 sll a0,16
+0+50009c <[^>]*> f728 4c01 addiu a0,18209
+0+5000a0 <[^>]*> f060 6c16 li a0,118
+0+5000a4 <[^>]*> f400 3480 sll a0,16
+0+5000a8 <[^>]*> f02b 4c01 addiu a0,22561
+0+5000ac <[^>]*> f060 6c16 li a0,118
+0+5000b0 <[^>]*> f400 3480 sll a0,16
+0+5000b4 <[^>]*> f40b 4c0a addiu a0,23562
+0+5000b8 <[^>]*> f060 6c16 li a0,118
+0+5000bc <[^>]*> f400 3480 sll a0,16
+0+5000c0 <[^>]*> f42a 4c11 addiu a0,21553
+0+5000c4 <[^>]*> f060 6c16 li a0,118
+0+5000c8 <[^>]*> f400 3480 sll a0,16
+0+5000cc <[^>]*> f40b 4c09 addiu a0,23561
+0+5000d0 <[^>]*> 6c01 li a0,1
+0+5000d2 <[^>]*> f400 3480 sll a0,16
+0+5000d6 <[^>]*> f010 4c00 addiu a0,-32768
+0+5000da <[^>]*> f060 6c06 li a0,102
+0+5000de <[^>]*> f400 3480 sll a0,16
+0+5000e2 <[^>]*> f338 4c00 addiu a0,-15584
+0+5000e6 <[^>]*> f060 6c06 li a0,102
+0+5000ea <[^>]*> f400 3480 sll a0,16
+0+5000ee <[^>]*> f338 4c04 addiu a0,-15580
+0+5000f2 <[^>]*> f060 6c06 li a0,102
+0+5000f6 <[^>]*> f400 3480 sll a0,16
+0+5000fa <[^>]*> f338 4c10 addiu a0,-15568
+0+5000fe <[^>]*> f060 6c06 li a0,102
+0+500102 <[^>]*> f400 3480 sll a0,16
+0+500106 <[^>]*> f738 4c00 addiu a0,-14560
+0+50010a <[^>]*> f060 6c17 li a0,119
+0+50010e <[^>]*> f400 3480 sll a0,16
+0+500112 <[^>]*> f03b 4c00 addiu a0,-10208
+0+500116 <[^>]*> f060 6c17 li a0,119
+0+50011a <[^>]*> f400 3480 sll a0,16
+0+50011e <[^>]*> f41b 4c09 addiu a0,-9207
+0+500122 <[^>]*> f060 6c17 li a0,119
+0+500126 <[^>]*> f400 3480 sll a0,16
+0+50012a <[^>]*> f43a 4c10 addiu a0,-11216
+0+50012e <[^>]*> f060 6c17 li a0,119
+0+500132 <[^>]*> f400 3480 sll a0,16
+0+500136 <[^>]*> f41b 4c08 addiu a0,-9208
+0+50013a <[^>]*> 6c00 li a0,0
+0+50013c <[^>]*> f400 3480 sll a0,16
+0+500140 <[^>]*> f010 4c00 addiu a0,-32768
+0+500144 <[^>]*> f060 6c05 li a0,101
+0+500148 <[^>]*> f400 3480 sll a0,16
+0+50014c <[^>]*> f338 4c00 addiu a0,-15584
+0+500150 <[^>]*> f060 6c05 li a0,101
+0+500154 <[^>]*> f400 3480 sll a0,16
+0+500158 <[^>]*> f338 4c04 addiu a0,-15580
+0+50015c <[^>]*> f060 6c05 li a0,101
+0+500160 <[^>]*> f400 3480 sll a0,16
+0+500164 <[^>]*> f338 4c10 addiu a0,-15568
+0+500168 <[^>]*> f060 6c05 li a0,101
+0+50016c <[^>]*> f400 3480 sll a0,16
+0+500170 <[^>]*> f738 4c00 addiu a0,-14560
+0+500174 <[^>]*> f060 6c16 li a0,118
+0+500178 <[^>]*> f400 3480 sll a0,16
+0+50017c <[^>]*> f03b 4c00 addiu a0,-10208
+0+500180 <[^>]*> f060 6c16 li a0,118
+0+500184 <[^>]*> f400 3480 sll a0,16
+0+500188 <[^>]*> f41b 4c09 addiu a0,-9207
+0+50018c <[^>]*> f060 6c16 li a0,118
+0+500190 <[^>]*> f400 3480 sll a0,16
+0+500194 <[^>]*> f43a 4c10 addiu a0,-11216
+0+500198 <[^>]*> f060 6c16 li a0,118
+0+50019c <[^>]*> f400 3480 sll a0,16
+0+5001a0 <[^>]*> f41b 4c08 addiu a0,-9208
+0+5001a4 <[^>]*> 6c01 li a0,1
+0+5001a6 <[^>]*> f400 3480 sll a0,16
+0+5001aa <[^>]*> 4c00 addiu a0,0
+0+5001ac <[^>]*> f060 6c06 li a0,102
+0+5001b0 <[^>]*> f400 3480 sll a0,16
+0+5001b4 <[^>]*> f328 4c00 addiu a0,17184
+0+5001b8 <[^>]*> f060 6c06 li a0,102
+0+5001bc <[^>]*> f400 3480 sll a0,16
+0+5001c0 <[^>]*> f328 4c04 addiu a0,17188
+0+5001c4 <[^>]*> f060 6c06 li a0,102
+0+5001c8 <[^>]*> f400 3480 sll a0,16
+0+5001cc <[^>]*> f328 4c10 addiu a0,17200
+0+5001d0 <[^>]*> f060 6c06 li a0,102
+0+5001d4 <[^>]*> f400 3480 sll a0,16
+0+5001d8 <[^>]*> f728 4c00 addiu a0,18208
+0+5001dc <[^>]*> f060 6c17 li a0,119
+0+5001e0 <[^>]*> f400 3480 sll a0,16
+0+5001e4 <[^>]*> f02b 4c00 addiu a0,22560
+0+5001e8 <[^>]*> f060 6c17 li a0,119
+0+5001ec <[^>]*> f400 3480 sll a0,16
+0+5001f0 <[^>]*> f40b 4c09 addiu a0,23561
+0+5001f4 <[^>]*> f060 6c17 li a0,119
+0+5001f8 <[^>]*> f400 3480 sll a0,16
+0+5001fc <[^>]*> f42a 4c10 addiu a0,21552
+0+500200 <[^>]*> f060 6c17 li a0,119
+0+500204 <[^>]*> f400 3480 sll a0,16
+0+500208 <[^>]*> f40b 4c08 addiu a0,23560
+0+50020c <[^>]*> 6c02 li a0,2
+0+50020e <[^>]*> f400 3480 sll a0,16
+0+500212 <[^>]*> f5b4 4c05 addiu a0,-23131
+0+500216 <[^>]*> f060 6c07 li a0,103
+0+50021a <[^>]*> f400 3480 sll a0,16
+0+50021e <[^>]*> f0dd 4c05 addiu a0,-5947
+0+500222 <[^>]*> f060 6c07 li a0,103
+0+500226 <[^>]*> f400 3480 sll a0,16
+0+50022a <[^>]*> f0dd 4c09 addiu a0,-5943
+0+50022e <[^>]*> f060 6c07 li a0,103
+0+500232 <[^>]*> f400 3480 sll a0,16
+0+500236 <[^>]*> f0dd 4c15 addiu a0,-5931
+0+50023a <[^>]*> f060 6c07 li a0,103
+0+50023e <[^>]*> f400 3480 sll a0,16
+0+500242 <[^>]*> f4dd 4c05 addiu a0,-4923
+0+500246 <[^>]*> f060 6c18 li a0,120
+0+50024a <[^>]*> f400 3480 sll a0,16
+0+50024e <[^>]*> f5df 4c05 addiu a0,-571
+0+500252 <[^>]*> f060 6c18 li a0,120
+0+500256 <[^>]*> f400 3480 sll a0,16
+0+50025a <[^>]*> f1a0 4c0e addiu a0,430
+0+50025e <[^>]*> f060 6c18 li a0,120
+0+500262 <[^>]*> f400 3480 sll a0,16
+0+500266 <[^>]*> f1df 4c15 addiu a0,-1579
+0+50026a <[^>]*> f060 6c18 li a0,120
+0+50026e <[^>]*> f400 3480 sll a0,16
+0+500272 <[^>]*> f1a0 4c0d addiu a0,429
+0+500276 <[^>]*> 6d00 li a1,0
+0+500278 <[^>]*> f400 35a0 sll a1,16
+0+50027c <[^>]*> 9d80 lw a0,0\(a1\)
+0+50027e <[^>]*> f060 6d05 li a1,101
+0+500282 <[^>]*> f400 35a0 sll a1,16
+0+500286 <[^>]*> f060 9d85 lw a0,101\(a1\)
+0+50028a <[^>]*> f060 6d05 li a1,101
+0+50028e <[^>]*> f400 35a0 sll a1,16
+0+500292 <[^>]*> f060 9d85 lw a0,101\(a1\)
+0+500296 <[^>]*> f060 6d05 li a1,101
+0+50029a <[^>]*> f400 35a0 sll a1,16
+0+50029e <[^>]*> f328 9d90 lw a0,17200\(a1\)
+0+5002a2 <[^>]*> f060 6d05 li a1,101
+0+5002a6 <[^>]*> f400 35a0 sll a1,16
+0+5002aa <[^>]*> f728 9d80 lw a0,18208\(a1\)
+0+5002ae <[^>]*> f060 6d16 li a1,118
+0+5002b2 <[^>]*> f400 35a0 sll a1,16
+0+5002b6 <[^>]*> f02b 9d80 lw a0,22560\(a1\)
+0+5002ba <[^>]*> f060 6d16 li a1,118
+0+5002be <[^>]*> f400 35a0 sll a1,16
+0+5002c2 <[^>]*> f40b 9d89 lw a0,23561\(a1\)
+0+5002c6 <[^>]*> f060 6d16 li a1,118
+0+5002ca <[^>]*> f400 35a0 sll a1,16
+0+5002ce <[^>]*> f42a 9d90 lw a0,21552\(a1\)
+0+5002d2 <[^>]*> f060 6d16 li a1,118
+0+5002d6 <[^>]*> f400 35a0 sll a1,16
+0+5002da <[^>]*> f40b 9d88 lw a0,23560\(a1\)
+0+5002de <[^>]*> 6d00 li a1,0
+0+5002e0 <[^>]*> f400 35a0 sll a1,16
+0+5002e4 <[^>]*> f000 9d81 lw a0,1\(a1\)
+0+5002e8 <[^>]*> f060 6d05 li a1,101
+0+5002ec <[^>]*> f400 35a0 sll a1,16
+0+5002f0 <[^>]*> f328 9d81 lw a0,17185\(a1\)
+0+5002f4 <[^>]*> f060 6d05 li a1,101
+0+5002f8 <[^>]*> f400 35a0 sll a1,16
+0+5002fc <[^>]*> f328 9d85 lw a0,17189\(a1\)
+0+500300 <[^>]*> f060 6d05 li a1,101
+0+500304 <[^>]*> f400 35a0 sll a1,16
+0+500308 <[^>]*> f328 9d91 lw a0,17201\(a1\)
+0+50030c <[^>]*> f060 6d05 li a1,101
+0+500310 <[^>]*> f400 35a0 sll a1,16
+0+500314 <[^>]*> f728 9d81 lw a0,18209\(a1\)
+0+500318 <[^>]*> f060 6d16 li a1,118
+0+50031c <[^>]*> f400 35a0 sll a1,16
+0+500320 <[^>]*> f02b 9d81 lw a0,22561\(a1\)
+0+500324 <[^>]*> f060 6d16 li a1,118
+0+500328 <[^>]*> f400 35a0 sll a1,16
+0+50032c <[^>]*> f40b 9d8a lw a0,23562\(a1\)
+0+500330 <[^>]*> f060 6d16 li a1,118
+0+500334 <[^>]*> f400 35a0 sll a1,16
+0+500338 <[^>]*> f42a 9d91 lw a0,21553\(a1\)
+0+50033c <[^>]*> f060 6d16 li a1,118
+0+500340 <[^>]*> f400 35a0 sll a1,16
+0+500344 <[^>]*> f40b 9d89 lw a0,23561\(a1\)
+0+500348 <[^>]*> 6d01 li a1,1
+0+50034a <[^>]*> f400 35a0 sll a1,16
+0+50034e <[^>]*> f010 9d80 lw a0,-32768\(a1\)
+0+500352 <[^>]*> f060 6d06 li a1,102
+0+500356 <[^>]*> f400 35a0 sll a1,16
+0+50035a <[^>]*> f338 9d80 lw a0,-15584\(a1\)
+0+50035e <[^>]*> f060 6d06 li a1,102
+0+500362 <[^>]*> f400 35a0 sll a1,16
+0+500366 <[^>]*> f338 9d84 lw a0,-15580\(a1\)
+0+50036a <[^>]*> f060 6d06 li a1,102
+0+50036e <[^>]*> f400 35a0 sll a1,16
+0+500372 <[^>]*> f338 9d90 lw a0,-15568\(a1\)
+0+500376 <[^>]*> f060 6d06 li a1,102
+0+50037a <[^>]*> f400 35a0 sll a1,16
+0+50037e <[^>]*> f738 9d80 lw a0,-14560\(a1\)
+0+500382 <[^>]*> f060 6d17 li a1,119
+0+500386 <[^>]*> f400 35a0 sll a1,16
+0+50038a <[^>]*> f03b 9d80 lw a0,-10208\(a1\)
+0+50038e <[^>]*> f060 6d17 li a1,119
+0+500392 <[^>]*> f400 35a0 sll a1,16
+0+500396 <[^>]*> f41b 9d89 lw a0,-9207\(a1\)
+0+50039a <[^>]*> f060 6d17 li a1,119
+0+50039e <[^>]*> f400 35a0 sll a1,16
+0+5003a2 <[^>]*> f43a 9d90 lw a0,-11216\(a1\)
+0+5003a6 <[^>]*> f060 6d17 li a1,119
+0+5003aa <[^>]*> f400 35a0 sll a1,16
+0+5003ae <[^>]*> f41b 9d88 lw a0,-9208\(a1\)
+0+5003b2 <[^>]*> 6d00 li a1,0
+0+5003b4 <[^>]*> f400 35a0 sll a1,16
+0+5003b8 <[^>]*> f010 9d80 lw a0,-32768\(a1\)
+0+5003bc <[^>]*> f060 6d05 li a1,101
+0+5003c0 <[^>]*> f400 35a0 sll a1,16
+0+5003c4 <[^>]*> f338 9d80 lw a0,-15584\(a1\)
+0+5003c8 <[^>]*> f060 6d05 li a1,101
+0+5003cc <[^>]*> f400 35a0 sll a1,16
+0+5003d0 <[^>]*> f338 9d84 lw a0,-15580\(a1\)
+0+5003d4 <[^>]*> f060 6d05 li a1,101
+0+5003d8 <[^>]*> f400 35a0 sll a1,16
+0+5003dc <[^>]*> f338 9d90 lw a0,-15568\(a1\)
+0+5003e0 <[^>]*> f060 6d05 li a1,101
+0+5003e4 <[^>]*> f400 35a0 sll a1,16
+0+5003e8 <[^>]*> f738 9d80 lw a0,-14560\(a1\)
+0+5003ec <[^>]*> f060 6d16 li a1,118
+0+5003f0 <[^>]*> f400 35a0 sll a1,16
+0+5003f4 <[^>]*> f03b 9d80 lw a0,-10208\(a1\)
+0+5003f8 <[^>]*> f060 6d16 li a1,118
+0+5003fc <[^>]*> f400 35a0 sll a1,16
+0+500400 <[^>]*> f41b 9d89 lw a0,-9207\(a1\)
+0+500404 <[^>]*> f060 6d16 li a1,118
+0+500408 <[^>]*> f400 35a0 sll a1,16
+0+50040c <[^>]*> f43a 9d90 lw a0,-11216\(a1\)
+0+500410 <[^>]*> f060 6d16 li a1,118
+0+500414 <[^>]*> f400 35a0 sll a1,16
+0+500418 <[^>]*> f41b 9d88 lw a0,-9208\(a1\)
+0+50041c <[^>]*> 6d01 li a1,1
+0+50041e <[^>]*> f400 35a0 sll a1,16
+0+500422 <[^>]*> 9d80 lw a0,0\(a1\)
+0+500424 <[^>]*> f060 6d06 li a1,102
+0+500428 <[^>]*> f400 35a0 sll a1,16
+0+50042c <[^>]*> f328 9d80 lw a0,17184\(a1\)
+0+500430 <[^>]*> f060 6d06 li a1,102
+0+500434 <[^>]*> f400 35a0 sll a1,16
+0+500438 <[^>]*> f328 9d84 lw a0,17188\(a1\)
+0+50043c <[^>]*> f060 6d06 li a1,102
+0+500440 <[^>]*> f400 35a0 sll a1,16
+0+500444 <[^>]*> f328 9d90 lw a0,17200\(a1\)
+0+500448 <[^>]*> f060 6d06 li a1,102
+0+50044c <[^>]*> f400 35a0 sll a1,16
+0+500450 <[^>]*> f728 9d80 lw a0,18208\(a1\)
+0+500454 <[^>]*> f060 6d17 li a1,119
+0+500458 <[^>]*> f400 35a0 sll a1,16
+0+50045c <[^>]*> f02b 9d80 lw a0,22560\(a1\)
+0+500460 <[^>]*> f060 6d17 li a1,119
+0+500464 <[^>]*> f400 35a0 sll a1,16
+0+500468 <[^>]*> f40b 9d89 lw a0,23561\(a1\)
+0+50046c <[^>]*> f060 6d17 li a1,119
+0+500470 <[^>]*> f400 35a0 sll a1,16
+0+500474 <[^>]*> f42a 9d90 lw a0,21552\(a1\)
+0+500478 <[^>]*> f060 6d17 li a1,119
+0+50047c <[^>]*> f400 35a0 sll a1,16
+0+500480 <[^>]*> f40b 9d88 lw a0,23560\(a1\)
+0+500484 <[^>]*> 6d02 li a1,2
+0+500486 <[^>]*> f400 35a0 sll a1,16
+0+50048a <[^>]*> f5b4 9d85 lw a0,-23131\(a1\)
+0+50048e <[^>]*> f060 6d07 li a1,103
+0+500492 <[^>]*> f400 35a0 sll a1,16
+0+500496 <[^>]*> f0dd 9d85 lw a0,-5947\(a1\)
+0+50049a <[^>]*> f060 6d07 li a1,103
+0+50049e <[^>]*> f400 35a0 sll a1,16
+0+5004a2 <[^>]*> f0dd 9d89 lw a0,-5943\(a1\)
+0+5004a6 <[^>]*> f060 6d07 li a1,103
+0+5004aa <[^>]*> f400 35a0 sll a1,16
+0+5004ae <[^>]*> f0dd 9d95 lw a0,-5931\(a1\)
+0+5004b2 <[^>]*> f060 6d07 li a1,103
+0+5004b6 <[^>]*> f400 35a0 sll a1,16
+0+5004ba <[^>]*> f4dd 9d85 lw a0,-4923\(a1\)
+0+5004be <[^>]*> f060 6d18 li a1,120
+0+5004c2 <[^>]*> f400 35a0 sll a1,16
+0+5004c6 <[^>]*> f5df 9d85 lw a0,-571\(a1\)
+0+5004ca <[^>]*> f060 6d18 li a1,120
+0+5004ce <[^>]*> f400 35a0 sll a1,16
+0+5004d2 <[^>]*> f1a0 9d8e lw a0,430\(a1\)
+0+5004d6 <[^>]*> f060 6d18 li a1,120
+0+5004da <[^>]*> f400 35a0 sll a1,16
+0+5004de <[^>]*> f1df 9d95 lw a0,-1579\(a1\)
+0+5004e2 <[^>]*> f060 6d18 li a1,120
+0+5004e6 <[^>]*> f400 35a0 sll a1,16
+0+5004ea <[^>]*> f1a0 9d8d lw a0,429\(a1\)
+0+5004ee <[^>]*> 6500 nop
+#pass
diff -up --recursive --new-file binutils-2.15.94-20050214.macro/ld/testsuite/ld-mips-elf/mips16-hilo.ld binutils-2.15.94-20050214/ld/testsuite/ld-mips-elf/mips16-hilo.ld
--- binutils-2.15.94-20050214.macro/ld/testsuite/ld-mips-elf/mips16-hilo.ld 1970-01-01 00:00:00.000000000 +0000
+++ binutils-2.15.94-20050214/ld/testsuite/ld-mips-elf/mips16-hilo.ld 2005-02-12 04:02:43.000000000 +0000
@@ -0,0 +1,12 @@
+SECTIONS
+{
+ . = 0x0500000;
+ .text : { *(.text) }
+ . = 0x0654320;
+ .data : { *(.data) }
+ .sdata : { *(.sdata) }
+ . = 0x0765430;
+ .bss : { *(.bss) *(COMMON) }
+ .sbss : { *(.sbss) *(.scommon) }
+ /DISCARD/ : { *(*) }
+}
diff -up --recursive --new-file binutils-2.15.94-20050214.macro/ld/testsuite/ld-mips-elf/mips16-hilo.s binutils-2.15.94-20050214/ld/testsuite/ld-mips-elf/mips16-hilo.s
--- binutils-2.15.94-20050214.macro/ld/testsuite/ld-mips-elf/mips16-hilo.s 1970-01-01 00:00:00.000000000 +0000
+++ binutils-2.15.94-20050214/ld/testsuite/ld-mips-elf/mips16-hilo.s 2005-02-12 05:43:17.000000000 +0000
@@ -0,0 +1,14 @@
+ .data
+ .globl big_external_data_label
+big_external_data_label:
+ .fill 1000
+
+# align section end to 16-byte boundary for easier testing on multiple targets
+ .p2align 4
+
+ .globl small_external_data_label
+small_external_data_label:
+ .fill 1
+
+# align section end to 16-byte boundary for easier testing on multiple targets
+ .p2align 4