[binutils-gdb/binutils-2_26-branch] [AArch64] Fix errors rebasing the ARMv8.2 AT and system registers patch

[Matthew Wahab <mwahab at sourceware dot org>]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=efc71f65803c59464f331e0137b421ca493a9525

commit efc71f65803c59464f331e0137b421ca493a9525
Author: Matthew Wahab <matthew.wahab@arm.com>
Date:   Mon Dec 14 16:28:46 2015 +0000

    [AArch64] Fix errors rebasing the ARMv8.2 AT and system registers patch
    
    A mistake with rebasing the ARMv8.2 AT instruction patch left this part
    
    +  /* AT S1E1RP, AT S1E1WP.  Values are from aarch64_sys_regs_at.  */
    +  if ((reg->value == CPENS (0, C7, C9, 0)
    +       || reg->value == CPENS (0, C7, C9, 1))
    +      && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
    +    return FALSE;
    
    in aarch64_pstatefield_supported_p rather than in
    aarch64_sys_ins_reg_supported_p, where it was supposed to be.
    
    The patch adding support for id_aa64mmfr2_el1, also had the effect of
    removing a conditional branch in aarch64_sys_reg_supported_p.
    
    The effect of both of these is to suppress an error if some ARMv8.2
    system registers are used with the wrong -march settings.
    
    This patch fixes these mistakes.
    
    opcodes/
    2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
    
    	* aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
    	removed statement.
    	(aarch64_pstatefield_supported_p): Move feature checks for AT
    	registers ..
    	(aarch64_sys_ins_reg_supported_p): .. to here.
    
    Change-Id: I48783d118eaaf0f3312e8b08a8340ef7af4e36a4

Diff:
---
 opcodes/ChangeLog     |  8 ++++++++
 opcodes/aarch64-opc.c | 13 +++++++------
 2 files changed, 15 insertions(+), 6 deletions(-)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 992e5da..48d4300 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,13 @@
 2015-12-15  Matthew Wahab  <matthew.wahab@arm.com>
 
+	* aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
+	removed statement.
+	(aarch64_pstatefield_supported_p): Move feature checks for AT
+	registers ..
+	(aarch64_sys_ins_reg_supported_p): .. to here.
+
+2015-12-15  Matthew Wahab  <matthew.wahab@arm.com>
+
 	* aarch64-asm-2.c: Regenerate.
 	* aarch64-dis-2.c: Regenerate.
 	* aarch64-opc-2.c: Regenerate.
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 7d0ebb5..ececf23 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3198,6 +3198,7 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features,
        || reg->value == CPENC (3, 5, C14, C3, 1)
        || reg->value == CPENC (3, 5, C14, C3, 2))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
+    return FALSE;
 
   /* ARMv8.2 features.  */
 
@@ -3284,12 +3285,6 @@ aarch64_pstatefield_supported_p (const aarch64_feature_set features,
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
     return FALSE;
 
-  /* AT S1E1RP, AT S1E1WP.  Values are from aarch64_sys_regs_at.  */
-  if ((reg->value == CPENS (0, C7, C9, 0)
-       || reg->value == CPENS (0, C7, C9, 1))
-      && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
-    return FALSE;
-
   return TRUE;
 }
 
@@ -3389,6 +3384,12 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
     return FALSE;
 
+  /* AT S1E1RP, AT S1E1WP.  Values are from aarch64_sys_regs_at.  */
+  if ((reg->value == CPENS (0, C7, C9, 0)
+       || reg->value == CPENS (0, C7, C9, 1))
+      && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
+    return FALSE;
+
   return TRUE;
 }