This is the mail archive of the
binutils-cvs@sources.redhat.com
mailing list for the binutils project.
src include/opcode/i860.h bfd/cpu-i860.c bfd/e ...
- To: binutils-cvs at sourceware dot cygnus dot com
- Subject: src include/opcode/i860.h bfd/cpu-i860.c bfd/e ...
- From: jle at sourceware dot cygnus dot com
- Date: 28 Jul 2000 21:10:20 -0000
CVSROOT: /cvs/src
Module name: src
Changes by: jle@sourceware.cygnus.com 2000-07-28 14:10:20
Modified files:
include/opcode : i860.h
bfd : cpu-i860.c elf32-i860.c targets.c config.bfd
configure.in configure
opcodes : disassemble.c Makefile.in configure.in
configure
include : dis-asm.h
Added files:
include/elf : i860.h
opcodes : i860-dis.c
Log message:
2000-07-22 Jason Eckhardt <jle@cygnus.com>
* include/opcode/i860.h (btne, bte, bla): Changed these opcodes
to use sbroff ('r') instead of split16 ('s').
(J, K, L, M): New operand types for 16-bit aligned fields.
(ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to
use I, J, K, L, M instead of just I.
(T, U): New operand types for split 16-bit aligned fields.
(st.x): Changed these opcodes to use S, T, U instead of just S.
(andh, andnoth, orh, xorh): Deleted 3-register forms as they do not
exist on the i860.
(pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860.
(pfeq.ss, pfeq.dd): New opcodes.
(st.s): Fixed incorrect mask bits.
(fmlow): Fixed incorrect mask bits.
(fzchkl, pfzchkl): Fixed incorrect mask bits.
(faddz, pfaddz): Fixed incorrect mask bits.
(form, pform): Fixed incorrect mask bits.
(pfld.l): Fixed incorrect mask bits.
(fst.q): Fixed incorrect mask bits.
(all floating point opcodes): Fixed incorrect mask bits for
handling of dual bit.
* include/elf/i860.h: New file.
(elf_i860_reloc_type): Defined ELF32 i860 relocations.
* bfd/cpu-i860.c: Added comments.
* bfd/elf32-i860.c (TARGET_LITTLE_SYM): Defined to
bfd_elf32_i860_little_vec.
(TARGET_LITTLE_NAME): Defined to "elf32-i860-little".
(ELF_MAXPAGESIZE): Changed to 4096.
* bfd/targets.c (bfd_elf32_i860_little_vec): Declaration of
new target.
(bfd_target_vector): Added bfd_elf32_i860_little_vec.
* bfd/config.bfd (i860-stardent-sysv4*, i860-stardent-elf*): Added
config for little endian elf32 i860.
(targ_defvec): Define for the new config above
as "bfd_elf32_i860_little_vec".
(targ_selvecs): Define for the new config above
as "bfd_elf32_i860_vec bfd_elf32_i860_little_vec"
* bfd/configure.in (bfd_elf32_i860_little_vec): Added recognition
of new target vec.
* bfd/configure: Regenerated.
* opcodes/i860-dis.c: New file.
(print_insn_i860): New function.
(print_br_address): New function.
(sign_extend): New function.
(BITWISE_OP): New macro.
(I860_REG_PREFIX): New macro.
(grnames, frnames, crnames): New structures.
* opcodes/disassemble.c (ARCH_i860): Define.
(disassembler): Add check for bfd_arch_i860 to set disassemble
function to print_insn_i860.
* include/dis-asm.h (print_insn_i860): Add prototype.
* opcodes/Makefile.in (CFILES): Added i860-dis.c.
(ALL_MACHINES): Added i860-dis.lo.
(i860-dis.lo): New dependences.
* opcodes/configure.in: New bits for bfd_i860_arch.
* opcodes/configure: Regenerated.
Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/include/opcode/i860.h.diff?cvsroot=src&r1=1.1.1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/include/elf/i860.h.diff?cvsroot=src&r1=NONE&r2=1.1
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/bfd/cpu-i860.c.diff?cvsroot=src&r1=1.1.1.1&r2=1.2
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/bfd/elf32-i860.c.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/bfd/targets.c.diff?cvsroot=src&r1=1.25&r2=1.26
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/bfd/config.bfd.diff?cvsroot=src&r1=1.37&r2=1.38
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/bfd/configure.in.diff?cvsroot=src&r1=1.28&r2=1.29
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/bfd/configure.diff?cvsroot=src&r1=1.35&r2=1.36
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/i860-dis.c.diff?cvsroot=src&r1=NONE&r2=1.1
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/disassemble.c.diff?cvsroot=src&r1=1.16&r2=1.17
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/Makefile.in.diff?cvsroot=src&r1=1.23&r2=1.24
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/configure.in.diff?cvsroot=src&r1=1.11&r2=1.12
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/opcodes/configure.diff?cvsroot=src&r1=1.13&r2=1.14
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/include/dis-asm.h.diff?cvsroot=src&r1=1.16&r2=1.17