Re: [RFC] Systemtap translator support for hardware breakpoints on

[Roland McGrath <roland at redhat dot com>]

> On x86, you imply something akin to using one debug register monitoring
> "write" and the other monitoring "rw" for the same address, right?

Right.

> We did try this sometime back. The event does trigger an (one) exception
> and the only way to distinguish whether a 'read' happened is to look
> at the debug status register (DR6) and see if one or both bits are set,
> and take appropriate action.

Right, that's what I meant.

> Maybe, a better way to do it is to hide this complexity by stap taking
> care of using 2 DRs underneath -- 

That's exactly what I was suggesting.

> but there is no ironclad gurantee that
> 2 free debug registers are available for stap's use at all times.

Indeed, nor that there is one.


Thanks,
Roland