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Re: [PATCH] Linux Kernel Markers
- From: Alan Cox <alan at lxorguk dot ukuu dot org dot uk>
- To: karim at opersys dot com
- Cc: Mathieu Desnoyers <compudj at krystal dot dyndns dot org>, Martin Bligh <mbligh at google dot com>, prasanna at in dot ibm dot com, Andrew Morton <akpm at osdl dot org>, "Frank Ch. Eigler" <fche at redhat dot com>, Ingo Molnar <mingo at elte dot hu>, Paul Mundt <lethal at linux-sh dot org>, linux-kernel <linux-kernel at vger dot kernel dot org>, Jes Sorensen <jes at sgi dot com>, Tom Zanussi <zanussi at us dot ibm dot com>, Richard J Moore <richardj_moore at uk dot ibm dot com>, Michel Dagenais <michel dot dagenais at polymtl dot ca>, Christoph Hellwig <hch at infradead dot org>, Greg Kroah-Hartman <gregkh at suse dot de>, Thomas Gleixner <tglx at linutronix dot de>, William Cohen <wcohen at redhat dot com>, ltt-dev at shafik dot org, systemtap at sources dot redhat dot com
- Date: Wed, 20 Sep 2006 11:44:29 +0100
- Subject: Re: [PATCH] Linux Kernel Markers
- References: <20060918234502.GA197@Krystal> <20060919081124.GA30394@elte.hu> <451008AC.firstname.lastname@example.org> <20060919154612.GU3951@redhat.com> <4510151B.email@example.com> <firstname.lastname@example.org> <45101DBA.email@example.com> <20060919063821.GB23836@in.ibm.com> <firstname.lastname@example.org> <20060919175405.GC26339@Krystal> <email@example.com> <451090E7.firstname.lastname@example.org>
Ar Maw, 2006-09-19 am 20:52 -0400, ysgrifennodd Karim Yaghmour:
> a) the errata & a possible thread having an IP leading back within (not
> at the start of) the range to be replaced.
> b) the errata & replacing single instruction with single instruction of
> same size.
Intel don't distinguish. Richard's reply later in the thread answers a
lot more including what Intels architecture team said about int3 being a
specific safe case for soem reason
> I was vaguely aware of the issue on x86. Do you know if this applies the
> same on other achitectures?
I wouldn't know.
> Also, this is SMP-only, right? (Not that single UP matters for desktop
> anymore, but just checking.)
There are some uniprocessor errata but I cannot see how you could patch
code, somehow take an interrupt (or return from one) without executing a
serializing instruction, so I likewise think its SMP only.
> Any pointers to the errata?
developer.intel.com 'specification update' documents (which are always