# Load libraries
load libcache.la cache_component_library
load libcgencpu.la cgen_component_library
load libmmu.la mmu_component_library
load libinterrupt.la interrupt_component_library

# Allocate components
new hw-cpu-crisv32 cpu2
new hw-mmu-crisv32 insn-mmu2
new hw-mmu-crisv32 data-mmu2
new hw-cache-dummy icache
new hw-cache-dummy dcache
new hw-cache-dummy icache2
new hw-cache-dummy dcache2
new hw-interrupt-crisv32 irq2
new hw-timer-crisv32 timer2

# Global connections
connect-pin hw-reset-net output-0 -> cpu2 reset!
connect-pin hw-reset-net output-1 -> insn-mmu2 reset 
connect-pin hw-reset-net output-2 -> data-mmu2 reset
connect-pin yield-net output-0 -> cpu2 yield

# Scheduler
connect-pin target-sched 0-event -> cpu2 step!
connect-pin target-sched 0-control <- cpu2 step-cycles
connect-pin target-sched time-query <- cpu2 time-query
connect-pin target-sched time-high -> cpu2 time-high
connect-pin target-sched time-low -> cpu2 time-low

# Override settings from linux.conf
disconnect-bus insn-mmu all cpu-mapper access-port
disconnect-bus data-mmu all cpu-mapper access-port
connect-bus insn-mmu all icache upstream
connect-bus data-mmu all dcache upstream
set cpu crisv32-start-address 0

# CPU
set cpu2 step-insn-count 10000
set cpu2 engine-type pbb
set cpu2 endian little
set cpu2 crisv32-start-address 0

# MMUs
connect-bus insn-mmu2 all icache2 upstream
connect-bus data-mmu2 all dcache2 upstream
connect-bus cpu2 insn-memory insn-mmu2 access-port
connect-pin cpu2 user -> insn-mmu2 user
connect-pin cpu2 pid -> insn-mmu2 pid
connect-pin cpu2 enable-insn-mmu -> insn-mmu2 enable
connect-bus cpu2 support-function-register-bank-1 insn-mmu2 registers
connect-pin insn-mmu2 refill_fault -> cpu2 insn-refill-fault
connect-pin insn-mmu2 invalid_fault -> cpu2 insn-invalidaddr-fault
connect-pin insn-mmu2 access_fault -> cpu2 insn-access-fault
connect-pin insn-mmu2 ex_fault -> cpu2 insn-ex-fault
connect-pin insn-mmu2 fault_address -> cpu2 insn-fault-address
set insn-mmu2 accesses-are-fetches true
connect-bus cpu2 data-memory data-mmu2 access-port
connect-pin cpu2 user -> data-mmu2 user
connect-pin cpu2 pid -> data-mmu2 pid
connect-pin cpu2 enable-data-mmu -> data-mmu2 enable
connect-bus cpu2 support-function-register-bank-2 data-mmu2 registers
connect-pin data-mmu2 refill_fault -> cpu2 data-refill-fault
connect-pin data-mmu2 invalid_fault -> cpu2 data-invalidaddr-fault
connect-pin data-mmu2 access_fault -> cpu2 data-access-fault
connect-pin data-mmu2 we_fault -> cpu2 data-we-fault
connect-pin data-mmu2 fault_address -> cpu2 data-fault-address

# Cache
connect-bus icache downstream cpu-mapper access-port
connect-bus dcache downstream cpu-mapper access-port
connect-pin dcache write_miss -> cpu dcache-write-miss
connect-pin cpu dcache-abort-write -> dcache abort
connect-bus icache2 downstream cpu-mapper access-port
connect-bus dcache2 downstream cpu-mapper access-port
connect-pin dcache2 write_miss -> cpu2 dcache-write-miss
connect-pin cpu2 dcache-abort-write -> dcache2 abort
connect-pin dcache write_out -> dcache2 write_in
connect-pin dcache2 write_out -> dcache write_in

# Timer
connect-pin hw-reset-net output-0 -> timer2 reset
connect-pin timer2 timer0-control -> target-sched 3-control
connect-pin target-sched 3-event -> timer2 timer0-event
connect-pin timer2 timer1-control -> target-sched 4-control
connect-pin target-sched 4-event -> timer2 timer1-event
connect-pin timer2 trig-control -> target-sched 5-control
connect-pin target-sched 5-event -> timer2 trig-event
connect-pin timer2 watchdog-control -> target-sched 6-control
connect-pin target-sched 6-event -> timer2 watchdog-event
connect-pin timer2 nmi -> cpu2 nmi
set timer2 slowdown 2
set timer2 speedup 1
set timer2 nmi_polarity 1

# Interrupt
connect-pin hw-reset-net output-0 -> irq2 reset
connect-pin dma0 irq_out -> irq2 irq6
connect-pin dma1 irq_out -> irq2 irq7
connect-pin dma2 irq_out -> irq2 irq8
connect-pin dma3 irq_out -> irq2 irq9
connect-pin dma4 irq_out -> irq2 irq10
connect-pin dma5 irq_out -> irq2 irq11
connect-pin dma6 irq_out -> irq2 irq12
connect-pin dma7 irq_out -> irq2 irq13
connect-pin dma8 irq_out -> irq2 irq14
connect-pin dma9 irq_out -> irq2 irq15
connect-pin ser0 irq_out -> irq2 irq19
connect-pin ser1 irq_out -> irq2 irq20
connect-pin ser2 irq_out -> irq2 irq21
connect-pin ser3 irq_out -> irq2 irq22
connect-pin timer2 irq -> irq2 irq26
connect-pin irq2 ipi_out -> irq2 irq30
connect-pin irq ipi_out -> irq irq30
connect-pin irq2 irq_out -> cpu2 irq
connect-bus cpu2 irq_vector irq2 irq_vector
set irq2 polarity 1

# Memory map
connect-bus cpu-mapper irq2:[0xb005c000,0xb005dfff] irq2 registers
connect-bus cpu-mapper timer2:[0xb005e000,0xb005ffff] timer2 registers