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[PATCH 3/3] arc: Fix crt0.S for cores without barrel shifter

crt0.S for ARC used to use instruction "asr.f lp_count, r3, 2" for all cores
except ARC601. However instructions which shift more than 1 bit are
optional, so this crt0.S didn't worked for all ARC cores.

Luckily this is a shift just by 2 bits on all occassions, so fix is trivial
- use two single-bit shifts.


2016-04-29  Anton Kolesov  <>

	* arc/crt0.S: Fix support for processors without barrel-shifter.

Signed-off-by: Anton Kolesov <>
 libgloss/arc/crt0.S | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/libgloss/arc/crt0.S b/libgloss/arc/crt0.S
index fdcdefa..3b80184 100644
--- a/libgloss/arc/crt0.S
+++ b/libgloss/arc/crt0.S
@@ -136,7 +136,12 @@ __start:
 	mov_s	r2, @__sbss_start	; r2 = start of the bss section
 	sub	r3, @_end, r2		; r3 = size of the bss section in bytes
 	; set up the loop counter register to the size (in words) of the bss section
+#if defined (__ARC_BARREL_SHIFTER__)
 	asr.f	lp_count, r3, 2
+	asr_s	r13, r3
+	asr.f	lp_count, r13
 #if defined (__ARC600__)
 	; loop to zero out the bss.  Enter loop only if lp_count != 0
 	lpnz	@.Lend_zbss

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