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Build libxil.a and xil-*crt0.o for powerpc-xilinx-eabi
- From: Michael Eager <eager at eagercon dot com>
- To: Newlib <newlib at sourceware dot org>
- Date: Wed, 06 May 2009 17:06:30 -0700
- Subject: Build libxil.a and xil-*crt0.o for powerpc-xilinx-eabi
Attached is a patch which adds xil-crt0.S, source
for xil-*crt0.o, and builds libxil.a. For Xilinx
PowerPC 405/440.
--
Michael Eager eager@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
2009-05-06 Michael Eager <eager@eagercon.com>
* libgloss/rs6000/Makefile.in: Build libxil.a.
* libgloss/rs6000/xil-crt0.s: New. Crt0 file for powerpc-xilinx-eabi.
diff -urNp --exclude '*.swp' --exclude DEV-PHASE --exclude .svn newlib-orig/libgloss/rs6000/Makefile.in newlib/libgloss/rs6000/Makefile.in
--- newlib-orig/libgloss/rs6000/Makefile.in 2009-05-06 08:42:16.000000000 -0700
+++ newlib/libgloss/rs6000/Makefile.in 2009-05-06 08:42:35.000000000 -0700
@@ -123,7 +123,7 @@ MBX_INSTALL = install-mbx
XIL_SCRIPTS = xilinx.ld xilinx440.ld
XIL_SPECS =
-XIL_CRT0 =
+XIL_CRT0 = xil-crt0.o xil-pgcrt0.o xil-sim-crt0.o xil-sim-pgcrt0.o
XIL_BSP = libxil.a
XIL_OBJS = open.o close.o lseek.o sbrk.o read.o write.o print.o
XIL_TEST = xil-test
@@ -312,6 +312,18 @@ mbx-inbyte.o: mbx-inbyte.c
mbx-outbyte.o: mbx-outbyte.c
mbx-print.o: mbx-print.c
+xil-crt0.o: xil-crt0.S
+ ${CC} -c -o $@ $<
+
+xil-pgcrt0.o: xil-crt0.S
+ ${CC} -c -DPROFILING -o $@ $<
+
+xil-sim-crt0.o: xil-crt0.S
+ ${CC} -c -DSIMULATOR -o $@ $<
+
+xil-sim-pgcrt0.o: xil-crt0.S
+ ${CC} -c -DSIMULATOR -DPROFILING -o $@ $<
+
sol-cfuncs.o: sol-cfuncs.c
sol-syscall.o: sol-syscall.S
@@ -367,8 +379,8 @@ install-mbx:
set -e; for x in ${MBX_SCRIPTS} ${MBX_SPECS}; do ${INSTALL_DATA} $(srcdir)/$$x $(DESTDIR)${tooldir}/lib${MULTISUBDIR}/$$x; done
install-xil:
- set -e; for x in ${XIL_CRT0} ${XIL_BSP}; do ${INSTALL_DATA} $$x $(DESTDIR)${tooldir}/lib${MULTISUBDIR}/$$x; done
- set -e; for x in ${XIL_SCRIPTS} ${XIL_SPECS}; do ${INSTALL_DATA} $(srcdir)/$$x $(DESTDIR)${tooldir}/lib${MULTISUBDIR}/$$x; done
+ set -e; for x in ${XIL_CRT0} ${XIL_BSP}; do ${INSTALL_DATA} $$x $(DESTDIR)${tooldir}/lib/$$x; done
+ set -e; for x in ${XIL_SCRIPTS} ${XIL_SPECS}; do ${INSTALL_DATA} $(srcdir)/$$x $(DESTDIR)${tooldir}/lib/$$x; done
doc:
info:
diff -urNp --exclude '*.swp' --exclude DEV-PHASE --exclude .svn newlib-orig/libgloss/rs6000/xil-crt0.S newlib/libgloss/rs6000/xil-crt0.S
--- newlib-orig/libgloss/rs6000/xil-crt0.S 1969-12-31 16:00:00.000000000 -0800
+++ newlib/libgloss/rs6000/xil-crt0.S 2009-05-06 08:42:35.000000000 -0700
@@ -0,0 +1,178 @@
+/*-----------------------------------------------------------------------------
+//
+// Copyright (c) 2004, 2009 Xilinx, Inc. All rights reserved.
+//
+// Xilinx, Inc.
+// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
+// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
+// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
+// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
+// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
+// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
+// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
+// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
+// AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+//---------------------------------------------------------------------------*/
+
+ .file "xil-crt0.S"
+ .section ".got2","aw"
+ .align 2
+
+.LCTOC1 = . + 32768
+
+.Lsbss_start = .-.LCTOC1
+ .long __sbss_start
+
+.Lsbss_end = .-.LCTOC1
+ .long __sbss_end
+
+.Lbss_start = .-.LCTOC1
+ .long __bss_start
+
+.Lbss_end = .-.LCTOC1
+ .long __bss_end
+
+.Lstack = .-.LCTOC1
+ .long __stack
+
+.Lsda = .-.LCTOC1
+ .long _SDA_BASE_ /* address of the first small data area */
+
+.Lsda2 = .-.LCTOC1
+ .long _SDA2_BASE_ /* address of the second small data area */
+
+
+ .text
+ .globl _start
+_start:
+ bl __cpu_init /* Initialize the CPU first (BSP provides this) */
+
+ lis 5,.LCTOC1@h
+ ori 5,5,.LCTOC1@l
+
+ lwz 13,.Lsda(5) /* load r13 with _SDA_BASE_ address */
+ lwz 2,.Lsda2(5) /* load r2 with _SDA2_BASE_ address */
+
+#ifndef SIMULATOR
+ /* clear sbss */
+ lwz 6,.Lsbss_start(5) /* calculate beginning of the SBSS */
+ lwz 7,.Lsbss_end(5) /* calculate end of the SBSS */
+
+ cmplw 1,6,7
+ bc 4,4,.Lenclsbss /* If no SBSS, no clearing required */
+
+ li 0,0 /* zero to clear memory */
+ subf 8,6,7 /* number of bytes to zero */
+ srwi. 9,8,2 /* number of words to zero */
+ beq .Lstbyteloopsbss /* Check if the number of bytes was less than 4 */
+ mtctr 9
+ addi 6,6,-4 /* adjust so we can use stwu */
+.Lloopsbss:
+ stwu 0,4(6) /* zero sbss */
+ bdnz .Lloopsbss
+
+.Lstbyteloopsbss:
+ andi. 9,8,3 /* Calculate how many trailing bytes we have */
+ beq 0,.Lenclsbss
+ mtctr 9
+ addi 6,6,-1 /* adjust, so we can use stbu */
+
+.Lbyteloopsbss:
+ stbu 0,1(6)
+ bdnz .Lbyteloopsbss
+
+.Lenclsbss:
+.Lstclbss:
+
+ /* clear bss */
+ lwz 6,.Lbss_start(5) /* calculate beginning of the BSS */
+ lwz 7,.Lbss_end(5) /* calculate end of the BSS */
+
+ cmplw 1,6,7
+ bc 4,4,.Lenclbss /* If no BSS, no clearing required */
+
+ li 0,0 /* zero to clear memory */
+ subf 8,6,7 /* number of bytes to zero */
+ srwi. 9,8,2 /* number of words to zero */
+ beq .Lstbyteloopbss /* Check if the number of bytes was less than 4 */
+ mtctr 9
+ addi 6,6,-4 /* adjust so we can use stwu */
+.Lloopbss:
+ stwu 0,4(6) /* zero bss */
+ bdnz .Lloopbss
+
+.Lstbyteloopbss:
+ andi. 9,8,3 /* Calculate how many trailing bytes we have */
+ beq 0,.Lenclbss /* If zero, we are done */
+ mtctr 9
+ addi 6,6,-1 /* adjust, so we can use stbu */
+
+.Lbyteloopbss:
+ stbu 0,1(6)
+ bdnz .Lbyteloopbss
+
+.Lenclbss:
+#endif /* SIMULATOR */
+
+ /* set stack pointer */
+ lwz 1,.Lstack(5) /* stack address */
+
+ /* set up initial stack frame */
+ addi 1,1,-8 /* location of back chain */
+ lis 0,0
+ stw 0,0(1) /* set end of back chain */
+
+ /* initialize base timer to zero */
+ mtspr 0x11c,0
+ mtspr 0x11d,0
+
+#ifdef HAVE_XFPU
+ /* On the Xilinx PPC405 and PPC440, the MSR
+ must be explicitly set to mark the prescence
+ of an FPU */
+ mfpvr 0
+ rlwinm 0,0,0,12,15
+ cmpwi 7,0,8192
+ mfmsr 0
+ ori 0,0,8192
+ beq- 7,fpu_init_done
+do_405:
+ oris 0,0,512
+fpu_init_done:
+ mtmsr 0
+#endif
+
+#ifdef PROFILING
+ /* Setup profiling stuff */
+ bl _profile_init
+#endif /* PROFILING */
+
+ /* Call __init */
+ bl __init
+
+ /* Let her rip */
+ bl main
+
+ /* Invoke the language cleanup functions */
+ bl __fini
+
+#ifdef PROFILING
+ /* Cleanup profiling stuff */
+ bl _profile_clean
+#endif /* PROFILING */
+
+ /* Call __init */
+ /* All done */
+ bl exit
+
+/* Trap has been removed for both simulation and hardware */
+ .globl _exit
+_exit:
+ b _exit
+
+.Lstart:
+ .size _start,.Lstart-_start
+