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[m32c] libgloss updates
- From: DJ Delorie <dj at redhat dot com>
- To: newlib at sourceware dot org
- Date: Wed, 24 Sep 2008 19:30:29 -0400
- Subject: [m32c] libgloss updates
Extra code in m32c's libgloss to support interrupt vector handling by
default, including a sample program that shows off this support.
Committed.
2008-09-24 DJ Delorie <dj@redhat.com>
* m32c/varvects.S: New.
* m32c/varvects.h: New.
* m32c/sample.c: New.
* m32c/Makefile.in: Add m32cgloss library support.
* m32c/crt0.S: Tweaks to support interrupts by default.
* m32c/m32c.tmpl: Likewise.
Index: m32c/Makefile.in
===================================================================
RCS file: /cvs/src/src/libgloss/m32c/Makefile.in,v
retrieving revision 1.3
diff -p -U3 -r1.3 m32c/Makefile.in
--- m32c/Makefile.in 19 Aug 2005 16:18:04 -0000 1.3
+++ m32c/Makefile.in 24 Sep 2008 23:28:47 -0000
@@ -1,4 +1,4 @@
-# Copyright (c) 2005 Red Hat Inc
+# Copyright (c) 2005,2008 Red Hat Inc
#
# The authors hereby grant permission to use, copy, modify, distribute,
# and license this software and its documentation for any purpose, provided
@@ -56,9 +56,11 @@ OBJCOPY = `if [ -f ${objroot}/../binutil
then echo ${objroot}/../binutils/objcopy ; \
else t='$(program_transform_name)'; echo objcopy | sed -e $$t ; fi`
+HEADERS = varvects.h
SCRIPTS = r8c.ld m16c.ld m32cm.ld m32c.ld m16cmon.ld m32cmon.ld sim8.ld sim16.ld sim24.ld
CRT = crt0.o crtn.o
SIM_BSP = libsim.a
+M32C_BSP = libm32cgloss.a
LIBNOSYS = ../libnosys/libnosys.a
SIM_OBJS = \
sbrk.o \
@@ -85,7 +87,8 @@ SIM_OBJS = \
link.o \
isatty.o \
abort.o
-
+M32C_OBJS = \
+ varvects.o
#### Host specific Makefile fragment comes in here.
@host_makefile_frag@
@@ -95,12 +98,16 @@ SIM_OBJS = \
.S.o:
$(CC) -Wa,-gdwarf2 -Wa,-I$(srcdir) $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -c $<
-all: $(CRT) $(SIM_BSP) $(SCRIPTS)
+all: $(CRT) $(SIM_BSP) $(M32C_BSP) $(SCRIPTS)
$(SIM_BSP): $(SIM_OBJS)
$(AR) $(ARFLAGS) $@ $?
$(RANLIB) $@
+$(M32C_BSP): $(M32C_OBJS)
+ $(AR) $(ARFLAGS) $@ $?
+ $(RANLIB) $@
+
# genscript parameters: srcdir name ramstart ramsize romstart romsize vecprefix
GDEP = $(srcdir)/m32c.tmpl $(srcdir)/genscript Makefile
@@ -167,12 +174,16 @@ unlink.o : $(SDEPS)
utime.o : $(SDEPS)
write.o : $(SDEPS)
-install: $(CRT) $(SIM_BSP) $(SCRIPTS)
- for c in $(CRT) $(SIM_BSP); do \
- $(INSTALL_DATA) $$c $(tooldir)/lib${MULTISUBDIR}/$$c ;\
+install: $(CRT) $(SIM_BSP) $(M32C_BSP) $(SCRIPTS)
+ for c in $(CRT) $(SIM_BSP) $(M32C_BSP); do \
+ $(INSTALL_DATA) $$c $(DESTDIR)$(tooldir)/lib${MULTISUBDIR}/$$c ;\
done
for c in $(SCRIPTS); do \
- $(INSTALL_DATA) $$c $(tooldir)/lib${MULTISUBDIR}/$$c ;\
+ $(INSTALL_DATA) $$c $(DESTDIR)$(tooldir)/lib${MULTISUBDIR}/$$c ;\
+ done
+ for c in $(HEADERS); do \
+ $(INSTALL_DATA) ${srcdir}/$$c \
+ $(DESTDIR)$(tooldir)/include/$$c ;\
done
clean mostlyclean:
Index: m32c/crt0.S
===================================================================
RCS file: /cvs/src/src/libgloss/m32c/crt0.S,v
retrieving revision 1.3
diff -p -U3 -r1.3 m32c/crt0.S
--- m32c/crt0.S 30 Jun 2006 21:55:23 -0000 1.3
+++ m32c/crt0.S 24 Sep 2008 23:28:47 -0000
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2005 Red Hat Incorporated.
+Copyright (c) 2005,2008 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -42,12 +42,15 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBI
#define ALIGN 2
#endif
+ .section ".resetvec","ax",@progbits
+ .long _start
+
.text
.global _start
_start:
.LFB2:
- fset U /* User stack */
+ fclr U /* One stack for user and interrupts */
ldc #__stack,sp
#ifdef A16
@@ -72,6 +75,14 @@ _start:
mov.w #0,r0
sstr.w
+#ifdef A16
+ ldc #%lo16(__var_vects),intbl
+ ldc #%hi16(__var_vects),intbh
+#else
+ ldc #__var_vects,intb
+#endif
+
+ fset I
jsr.a __m32c_init
jsr.a _main
Index: m32c/m32c.tmpl
===================================================================
RCS file: /cvs/src/src/libgloss/m32c/m32c.tmpl,v
retrieving revision 1.1
diff -p -U3 -r1.1 m32c/m32c.tmpl
--- m32c/m32c.tmpl 10 Aug 2005 20:29:33 -0000 1.1
+++ m32c/m32c.tmpl 24 Sep 2008 23:28:47 -0000
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2005 Red Hat Incorporated.
+Copyright (c) 2005,2008 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -35,6 +35,7 @@ OUTPUT_FORMAT("elf32-m32c", "elf32-m32c"
"elf32-m32c")
OUTPUT_ARCH(m32c)
ENTRY(_start)
+INPUT(-lm32cgloss)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
MEMORY {
@@ -132,6 +133,8 @@ SECTIONS
SORT(CONSTRUCTORS)
*(.data1)
*(.got.plt) *(.got)
+ PROVIDE (__var_vect_start = .);
+ *(.var_vects)
. = ALIGN(2);
_edata = .;
Index: m32c/sample.c
===================================================================
RCS file: m32c/sample.c
diff -N m32c/sample.c
--- m32c/sample.c 1 Jan 1970 00:00:00 -0000
+++ m32c/sample.c 24 Sep 2008 23:28:47 -0000
@@ -0,0 +1,159 @@
+/*
+
+Copyright (c) 2008 Red Hat Incorporated.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ The name of Red Hat Incorporated may not be used to endorse
+ or promote products derived from this software without specific
+ prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+/* This is a sample program that shows how to use a few of the
+ features of the M32C port of GCC, Binutils, and Newlib. */
+
+#include <varvects.h>
+
+typedef unsigned char byte;
+typedef unsigned short word;
+
+#define prcr (*(volatile byte *)0x000a)
+#define cm0 (*(volatile byte *)0x0006)
+#define cm1 (*(volatile byte *)0x0007)
+#define ocd (*(volatile byte *)0x000c)
+
+#ifdef __r8c_cpu__
+/* These are for the R8C/20 with LEDs on port P2 */
+
+#define tracr (*(volatile byte *)0x0100)
+#define traioc (*(volatile byte *)0x0101)
+#define tramr (*(volatile byte *)0x0102)
+#define trapre (*(volatile byte *)0x0103)
+#define tra (*(volatile byte *)0x0104)
+#define traic (*(volatile byte *)0x0056)
+
+#define pd2 (*(volatile byte *)0x00e6)
+#define p2 (*(volatile byte *)0x00e4)
+
+#define ivec_timer_ra 22
+#endif
+
+#ifdef __m32c_cpu__
+/* These are for the M32C/83 with LEDs on port P0 and P1 */
+
+#define ta0 (*(volatile word *)0x0346)
+#define ta0mr (*(volatile byte *)0x0356)
+#define tabsr (*(volatile byte *)0x0340)
+#define ta0ic (*(volatile byte *)0x006c)
+
+#define pd0 (*(volatile byte *)0x03e2)
+#define pd1 (*(volatile byte *)0x03e3)
+#define p0 (*(volatile byte *)0x03e0)
+#define p1 (*(volatile byte *)0x03e1)
+
+#define ivec_timer_a0 12
+#endif
+
+/* Newlib's exit() pulls in lots of other things. Main() should never
+ exit, but if it did, you could hard-reset the chip here. */
+void
+exit(int rv)
+{
+ while (1)
+ asm volatile ("");
+}
+
+#ifdef __r8c_cpu__
+/* The "constructor" attribute causes the startup code to call this
+ sometime before main() is called. */
+__attribute__((constructor))
+void
+fast_clock(void)
+{
+ asm("fclr I");
+ prcr = 1;
+ cm0 = 0x08;
+ cm1 = 0x38;
+ asm("nop");
+ asm("nop");
+ asm("nop");
+ asm("nop");
+ ocd = 0;
+ prcr = 0;
+ asm("fset I");
+}
+#endif
+
+/* We mark this volatile in case a non-interrupt function wants to
+ read it, else gcc may optimize away extra reads. */
+static volatile int tc = 1;
+
+/* The "interrupt" attribute changes the function entry/exit to
+ properly preserve any changed registers. */
+static void __attribute__((interrupt))
+timer_ra_interrupt()
+{
+ tc ++;
+#ifdef __r8c_cpu__
+ p2 = tc >> 4;
+#else
+ p1 = tc;
+ p0 = tc >> 8;
+#endif
+}
+
+main()
+{
+#ifdef __r8c_cpu__
+ pd2 = 0xff;
+
+ /* TIMER RA */
+ tracr = 0x00;
+ traioc = 0x00;
+ tramr = 0x00; /* timer mode, f1 */
+ trapre = 255; /* prescaler */
+ tra = 255; /* cycle count */
+
+ _set_var_vect (timer_ra_interrupt, ivec_timer_ra);
+ traic = 5;
+ tracr = 1;
+#endif
+
+#ifdef __m32c_cpu__
+ pd0 = 0xff;
+ pd1 = 0xff;
+
+ /* TIMER A0 */
+ ta0mr = 0x00; /* Timer A0 mode register */
+ ta0 = 65535; /* Timer A0 register */
+
+ _set_var_vect (timer_ra_interrupt, ivec_timer_a0);
+ ta0ic = 5;
+ tabsr = 0xff;
+#endif
+
+ /* main() must never return. */
+ while (1)
+ ;
+}
Index: m32c/varvects.S
===================================================================
RCS file: m32c/varvects.S
diff -N m32c/varvects.S
--- m32c/varvects.S 1 Jan 1970 00:00:00 -0000
+++ m32c/varvects.S 24 Sep 2008 23:28:47 -0000
@@ -0,0 +1,43 @@
+/*
+
+Copyright (c) 2008 Red Hat Incorporated.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ The name of Red Hat Incorporated may not be used to endorse
+ or promote products derived from this software without specific
+ prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+/* This works with varvects.h
+*/
+
+ .section ".var_vects","aw",@progbits
+ .global __var_vects
+ .type __var_vects,@object
+ .size __var_vects, 256
+__var_vects:
+ .zero 256
+
+ .text
Index: m32c/varvects.h
===================================================================
RCS file: m32c/varvects.h
diff -N m32c/varvects.h
--- m32c/varvects.h 1 Jan 1970 00:00:00 -0000
+++ m32c/varvects.h 24 Sep 2008 23:28:47 -0000
@@ -0,0 +1,54 @@
+/*
+
+Copyright (c) 2008 Red Hat Incorporated.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ The name of Red Hat Incorporated may not be used to endorse
+ or promote products derived from this software without specific
+ prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+/* This file defines the interface to the built-in variable vector
+ table in R8C/M16C/M32C chips. */
+
+#ifndef _VARVECTS_H_
+#define _VARVECTS_H_
+
+typedef void (*_m32c_interrupt_func)() __attribute__((mode(SI)));
+extern _m32c_interrupt_func _var_vects[];
+
+#if defined(__r8c_cpu__) || defined (__m16c_cpu__)
+
+#define _set_var_vect(f,n) \
+ { asm ("mov.w #%%lo16(%d0),__var_vects+%d1" : : "s" (f), "g" (n*4)); \
+ asm ("mov.w #%%hi16(%d0),__var_vects+%d1" : : "s" (f), "g" (n*4+2)); }
+
+#else
+
+#define _set_var_vect(f,n) \
+ _var_vects[n] = f
+
+#endif
+#endif