This is the mail archive of the libc-alpha@sourceware.org mailing list for the glibc project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [PATCH v2 7/6] [powerpc] Rename fesetenv_mode to fesetenv_control




On 9/19/19 2:14 PM, Paul A. Clarke wrote:
From: "Paul A. Clarke" <pc@us.ibm.com>

fesetenv_mode is used variously to write the FPSCR exception enable
bits and rounding mode bits.  These are referred to as the control
bits in the POWER ISA.  Change the name to be reflective of its
current and expected use, and match up well with fegetenv_control.

2019-09-19  Paul A. Clarke  <pc@us.ibm.com>

	* sysdeps/powerpc/fpu/fenv_libc.h (fesetenv_mode): Rename to
	fesetenv_control.
	* sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Accommodate
	rename of fesetenv_mode to fegetenv_control.
	* sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Likewise.
	* sysdeps/powerpc/fpu/fesetmode.c (fesetmode): Likewise.
	* sysdeps/powerpc/fpu/fenv_private.h (__libc_femergeenv_ppc): Likewise.
	(libc_feholdsetround_noex_ppc_ctx): Likewise.
---
This patch should've been tacked onto the series that I just posted
"[PATCH v2 0/6] Various FPSCR-related changes", thus the "7/6".  :-?
This is a new patch
OK.

Reviewed-By: Paul E Murphy <murphyp@linux.ibm.com>


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]