This is the mail archive of the
libc-alpha@sourceware.org
mailing list for the glibc project.
Re: [PATCH 4/4] [powerpc] fegetenv_status: simplify instruction generation
On 8/20/19 4:19 PM, Paul A. Clarke wrote:
From: "Paul A. Clarke" <pc@us.ibm.com>
fegetenv_status() wants to use the lighter weight instruction 'mffsl'
for reading the Floating-Point Status and Control Register (FPSCR).
It currently will use it directly if compiled '-mcpu=power9', and will
perform a runtime check (cpu_supports("arch_3_00")) otherwise.
Nicely, it turns out that the 'mffsl' instruction will decode to
'mffs' on architectures older than "arch_3_00" because the additional
bits set for 'mffsl' are "don't care" for 'mffs'. 'mffs' is a superset
of 'mffsl'.
That is a pretty neat trick. I would recommend inlining the above
comment. Otherwise, LGTM.
-#define fegetenv_status_ISA300() \
+#define fegetenv_status() \
({register double __fr; \
__asm__ __volatile__ ( \
".machine push; .machine \"power9\"; mffsl %0; .machine pop" \
@@ -45,18 +45,6 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden;
__fr; \
})