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[PATCH 0/2 v2] [powerpc] utilize faster method to get FPSCR
- From: "Paul A. Clarke" <pc at us dot ibm dot com>
- To: libc-alpha at sourceware dot org
- Cc: tuliom at ascii dot art dot br, fweimer at redhat dot com, joseph at codesourcery dot com
- Date: Thu, 13 Jun 2019 13:57:19 -0500
- Subject: [PATCH 0/2 v2] [powerpc] utilize faster method to get FPSCR
From: "Paul A. Clarke" <pc@us.ibm.com>
Using 'mffs' instruction to read the Floating Point Status Control Register
(FPSCR) can force a processor flush in some cases, with undesirable
performance impact. If the values of the bits in the FPSCR which force the
flush are not needed, an instruction that is new to POWER9 (ISA version 3.0),
'mffsl' can be used instead.
Paul A. Clarke (2):
[powerpc] add 'volatile' to asm
[powerpc] Use faster means to access FPSCR when possible in some cases
sysdeps/powerpc/bits/fenvinline.h | 22 +++++++++++++------
sysdeps/powerpc/fpu/fegetexcept.c | 2 +-
sysdeps/powerpc/fpu/fegetmode.c | 2 +-
sysdeps/powerpc/fpu/fenv_libc.h | 23 ++++++++++++++++++--
sysdeps/powerpc/fpu_control.h | 45 +++++++++++++++++++++------------------
5 files changed, 63 insertions(+), 31 deletions(-)
--
1.8.3.1