[PATCH 0/2] [powerpc] utilize faster method to get FPSCR

["Paul A. Clarke" <pc at us dot ibm dot com>]

From: "Paul A. Clarke" <pc@us.ibm.com>

Using 'mffs' instruction to read the Floating Point Status Control Register
(FPSCR) can force a processor flush in some cases, with undesirable
performance impact.  If the values of the bits in the FPSCR which force the
flush are not needed, an instruction that is new to POWER9 (ISA version 3.0),
'mffsl', can be used instead.

The first patch fixes an issue seen by Tulio with an earlier patch I sent
(not committed) where the compiler was deciding to eliminate some "asm"
sections.  Adding "volatile" solves this, and I took
the liberty of adding "volatile" to other similar "asm" sections.

The second patch combines a few patches I sent earlier (not committed),
some additional changes (fegetexcept) and includes changes to address a
suggestion by Adhemerval to make the optimizations immediately available
on POWER9 systems without having to compile for POWER9 by looking at the
HWCAP2 capabilities bits at runtime.

Paul A. Clarke (2):
  [powerpc] add 'volatile' to asm
  [powerpc] Use faster means to access FPSCR when possible in some cases

 sysdeps/powerpc/bits/fenvinline.h | 29 +++++++++++++++++++++------
 sysdeps/powerpc/fpu/fegetexcept.c |  2 +-
 sysdeps/powerpc/fpu/fegetmode.c   |  2 +-
 sysdeps/powerpc/fpu/fenv_libc.h   | 21 ++++++++++++++++++--
 sysdeps/powerpc/fpu_control.h     | 41 ++++++++++++++++++++-------------------
 5 files changed, 65 insertions(+), 30 deletions(-)

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1.8.3.1