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Re: [PATCH][AArch64] Add ifunc support for Ares
Hi Siddhesh,
> The falkor memcpy has a very specific quirk that reuses register names
> to optimise prefetcher usage so it may not necessarily work well with
> other implementations. Perhaps a new implementation similar to the
> stock memcpy but with vector registers would be more suitable for a
> __memcpy_simd.
Reusing registers does not matter on an out-of-order core since they are
renamed. But you're right that a generic SIMD memcpy could do better.
For example using LDP/STP of Q registers will be smaller and faster,
maybe even on Falkor.
Cheers,
Wilco