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Re: [PATCH][AArch64] Adjust writeback in non-zero memset
On 16/11/18 10:34 PM, Wilco Dijkstra wrote:
I ran it on Cortex-A72, and there isn't a performance difference on the memset bench
beyond measurement errors. On any out-of-order core address increments are
executed in parallel with loads/stores, ie. they have no measurable latency and so
their exact placement is irrelevant.
Thanks for the confirmation. Looks OK to me.