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* Adhemerval Zanella:
> diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
> index f4e0f5a2ed..80b3054cf8 100644
> --- a/sysdeps/x86/cpu-features.c
> +++ b/sysdeps/x86/cpu-features.c
> @@ -316,7 +316,13 @@ init_cpu_features (struct cpu_features *cpu_features)
> | bit_arch_Fast_Unaligned_Copy
> | bit_arch_Prefer_PMINUB_for_stringop);
> break;
> + }
>
> + /* Disable TSX on some Haswell processors to avoid TSX on kernels that
> + weren't updated with the latest microcode package (which disables
> + broken feature by default). */
> + switch (model)
> + {
> case 0x3f:
> /* Xeon E7 v3 with stepping >= 4 has working TSX. */
> if (stepping >= 4)
I think the change is okay as posted. It will need some testing in the
field because the newly selected implementations could have unexpected
performance drawbacks.
Thanks,
Florian
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