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Re: [PATCH] elf: Update GNU_PROPERTY_X86_XXX macros [BZ #23797]
On 10/20/18, Florian Weimer <fw@deneb.enyo.de> wrote:
> * H. J. Lu:
>
>> +#define GNU_PROPERTY_X86_ISA_1_CMOV (1U << 0)
>> +#define GNU_PROPERTY_X86_ISA_1_SSE (1U << 1)
>> +#define GNU_PROPERTY_X86_ISA_1_SSE2 (1U << 2)
>> +#define GNU_PROPERTY_X86_ISA_1_SSE3 (1U << 3)
>> +#define GNU_PROPERTY_X86_ISA_1_SSSE3 (1U << 4)
>> +#define GNU_PROPERTY_X86_ISA_1_SSE4_1 (1U << 5)
>> +#define GNU_PROPERTY_X86_ISA_1_SSE4_2 (1U << 6)
>> +#define GNU_PROPERTY_X86_ISA_1_AVX (1U << 7)
>> +#define GNU_PROPERTY_X86_ISA_1_AVX2 (1U << 8)
>> +#define GNU_PROPERTY_X86_ISA_1_FMA (1U << 9)
>> +#define GNU_PROPERTY_X86_ISA_1_AVX512F (1U << 10)
>> +#define GNU_PROPERTY_X86_ISA_1_AVX512CD (1U << 11)
>> +#define GNU_PROPERTY_X86_ISA_1_AVX512ER (1U << 12)
>> +#define GNU_PROPERTY_X86_ISA_1_AVX512PF (1U << 13)
>> +#define GNU_PROPERTY_X86_ISA_1_AVX512VL (1U << 14)
>> +#define GNU_PROPERTY_X86_ISA_1_AVX512DQ (1U << 15)
>> +#define GNU_PROPERTY_X86_ISA_1_AVX512BW (1U << 16)
>> +#define GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS (1U << 17)
>> +#define GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW (1U << 18)
>> +#define GNU_PROPERTY_X86_ISA_1_AVX512_BITALG (1U << 19)
>> +#define GNU_PROPERTY_X86_ISA_1_AVX512_IFMA (1U << 20)
>> +#define GNU_PROPERTY_X86_ISA_1_AVX512_VBMI (1U << 21)
>> +#define GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2 (1U << 22)
>> +#define GNU_PROPERTY_X86_ISA_1_AVX512_VNNI (1U << 23)
>
> What guides the selection of flags? Why is there CMOV (which
I defined them since I found they useful. We can add others.
> presumably implies FCMOV), but not CMPXCHG16B? What about TZCNT,
FCMPVcc is covered by the CMOV bit in CPUID. Please send what you
want to x86-64 psABI mailing list.
> which silently executed incorrectly if the CPU does not support it?
> Which FMA is FMA?
FMA is FMA from Intel SDM, not FMA4.
>> +#define GNU_PROPERTY_X86_FEATURE_2_X86 (1U << 0)
>> +#define GNU_PROPERTY_X86_FEATURE_2_X87 (1U << 1)
>> +#define GNU_PROPERTY_X86_FEATURE_2_MMX (1U << 2)
>> +#define GNU_PROPERTY_X86_FEATURE_2_XMM (1U << 3)
>> +#define GNU_PROPERTY_X86_FEATURE_2_YMM (1U << 4)
>> +#define GNU_PROPERTY_X86_FEATURE_2_ZMM (1U << 5)
>> +#define GNU_PROPERTY_X86_FEATURE_2_FXSR (1U << 6)
>> +#define GNU_PROPERTY_X86_FEATURE_2_XSAVE (1U << 7)
>> +#define GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT (1U << 8)
>> +#define GNU_PROPERTY_X86_FEATURE_2_XSAVEC (1U << 9)
>
> What's the difference between an ISA and a feature?
There is no exact boundary. SSE contains instructions with MMX registers.
The SSE ISA bit does't tell us if MMX registers are used.
--
H.J.