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Re: [PATCH] powerpc: Add enable exception bits
Joseph Myers <joseph@codesourcery.com> writes:
> On Wed, 27 Jun 2018, Tulio Magno Quites Machado Filho wrote:
>
>> The POWER ISA defines bits 56:60 (bits 24:28 in a 32-bit FPSCR) as
>> control for the 5 exceptions available: invalid operation, overflow,
>> underflow, zero divide and inexact.
>>
>> 2018-06-27 Tulio Magno Quites Machado Filho <tuliom@linux.ibm.com>
>>
>> * sysdeps/powerpc/bits/fenv.h [__USE_GNU]: Add
>> FE_INVALID_ENABLE, FE_OVERFLOW_ENABLE, FE_UNDERFLOW_ENABLE,
>> FE_DIVBYZERO_ENABLE and FE_INEXACT_ENABLE.
>
> I don't think it's the job of fenv.h to enumerate all bits in the FPSCR
> (that's more appropriate in fpu_control.h). Rather, it enumerates bits
> that are useful in arguments to the fenv.h interfaces. The *_ENABLE
> values are not relevant to the fenv.h interfaces, since feenableexcept
> (etc.) deals with converting the FE_* flag bits into appropriate values
> for enabling exception traps.
Ack.
Thanks!
--
Tulio Magno