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[PATCH 3/4] arm: Enable ARM mode for armv6 memchr
Current optimized armv6t2 memchr uses the NO_THUMB wrongly to
conditionalize thumb instruction usage. The flags is meant to be
defined before sysdep.h inclusion and to indicate the assembly
requires to build in ARM mode, not to check whether thumb is
enable or not. This patch fixes it by using the GCC provided
'__thumb__' instead.
Checked on arm-linux-gnueabihf (with -marm -march=armv6t2).
* sysdeps/arm/armv6t2/memchr.S (NO_THUMB): Check for __thumb__
instead.
---
ChangeLog | 3 +++
sysdeps/arm/armv6t2/memchr.S | 10 +++++-----
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/sysdeps/arm/armv6t2/memchr.S b/sysdeps/arm/armv6t2/memchr.S
index bdd385b..03b7f32 100644
--- a/sysdeps/arm/armv6t2/memchr.S
+++ b/sysdeps/arm/armv6t2/memchr.S
@@ -42,7 +42,7 @@
.syntax unified
.text
-#ifdef NO_THUMB
+#ifndef __thumb__
.arm
#else
.thumb
@@ -91,7 +91,7 @@ ENTRY(memchr)
15:
ldrd r4,r5, [r0],#8
-#ifndef NO_THUMB
+#ifdef __thumb__
subs r6, r6, #8
#endif
eor r4,r4, r1 @ Get it so that r4,r5 have 00's where the bytes match the target
@@ -100,7 +100,7 @@ ENTRY(memchr)
sel r4, r3, r7 @ bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION
uadd8 r5, r5, r7 @ Parallel add 0xff - sets the GE bits for anything that wasn't 0
sel r5, r4, r7 @ chained....bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION
-#ifndef NO_THUMB
+#ifdef __thumb__
cbnz r5, 60f
#else
cmp r5, #0
@@ -120,7 +120,7 @@ ENTRY(memchr)
and r2,r2,#7 @ Leave the count remaining as the number after the double words have been done
20:
-#ifndef NO_THUMB
+#ifdef __thumb__
cbz r2, 40f @ 0 length or hit the end already then not found
#else
cmp r2, #0
@@ -129,7 +129,7 @@ ENTRY(memchr)
21: @ Post aligned section, or just a short call
ldrb r3,[r0],#1
-#ifndef NO_THUMB
+#ifdef __thumb__
subs r2,r2,#1
eor r3,r3,r1 @ r3 = 0 if match - doesn't break flags from sub
cbz r3, 50f
--
2.7.4