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Re: riscv: fmax/fmin sNaN fix


Szabolcs Nagy <szabolcs.nagy@arm.com> writes:
> On 20/02/18 02:57, DJ Delorie wrote:
>> 
>> RISC-V's FPU follows the IEEE spec, not the POSIX spec.  This patch
>                             ^^^^^^^^^
> which one?
> (the next ieee revision will have different min/max operations)

FYI origin commit is:
https://github.com/riscv/riscv-glibc/pull/44/commits/ea8c2f70ed9685f8c220e09b28098fefbc96179a


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