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Re: Any reason ARM doesn't implement sysconf.c?
- From: Carlos O'Donell <carlos at redhat dot com>
- To: Richard Henderson <rth at twiddle dot net>
- Cc: Szabolcs Nagy <szabolcs dot nagy at arm dot com>, GNU C Library <libc-alpha at sourceware dot org>, Siddhesh Poyarekar <siddhesh at gotplt dot org>, nd at arm dot com
- Date: Tue, 31 Oct 2017 12:06:38 -0700
- Subject: Re: Any reason ARM doesn't implement sysconf.c?
- Authentication-results: sourceware.org; auth=none
- References: <67de1654-4545-1fde-e036-29a671ef731f@redhat.com> <59F8B2D8.8010303@arm.com>
On 10/31/2017 10:28 AM, Szabolcs Nagy wrote:
> On 31/10/17 15:30, Carlos O'Donell wrote:
>> Is there any reason ARM doesn't implement sysconf.c? Too much
>> hardware variance?
>>
>> We've had at least a few user reports over the last year that
>> things like sysconf (_SC_LEVEL1_DCACHE_SIZE); would be useful
>> to have.
>>
>
> i ok'd the patch
> https://sourceware.org/ml/libc-alpha/2017-10/msg00395.html
> but it seems it didnt get committed.
Richard,
Do you plan to commit your patch?
> i was complaining about it at first because i think it was a
> bad idea in the first place to introduce these undocumented
> sysconf variables in glibc and then let users misuse it..
> however there is a need to query the cache info that is
> available to userspace on aarch64 and this api seems to be
> what ppl expect.
>
> the problem is not hardware variance but that the sysconf
> names (l1/l2/l3 icache/dcache linesize) don't map to
> architecture names (minimal i/dcache linesize, writeback
> granule etc) that is userspace visible and have defined
> semantics, the l1/l2/l3 cache info is not userspace
> visible. (however Siddhesh wrote documentation for it now
> so this is fine)
>
>> On POWER this was generically fixed with some auxval entries
>> that were passed down to userspace.
--
Cheers,
Carlos.