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Re: [PATCH 1/3] Guess L1 cache linesize for aarch64
- From: Szabolcs Nagy <szabolcs dot nagy at arm dot com>
- To: Richard Henderson <rth at twiddle dot net>, libc-alpha at sourceware dot org
- Cc: nd at arm dot com, Marcus Shawcroft <marcus dot shawcroft at arm dot com>
- Date: Tue, 10 Oct 2017 11:19:50 +0100
- Subject: Re: [PATCH 1/3] Guess L1 cache linesize for aarch64
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On 08/06/17 23:57, Richard Henderson wrote:
> + /* Unfortunately, the registers that contain the actual cache info
> + (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux
> + kernel (though they need not have been). However, CTR_EL0 contains
> + the *minimum* linesize in the entire cache hierarchy, and is
> + accessible to userland, for use in __aarch64_sync_cache_range,
> + and it is a reasonable assumption that the L1 cache will have that
> + minimum line size. */
maybe
> + case _SC_LEVEL1_ICACHE_LINESIZE:
> + case _SC_LEVEL1_DCACHE_LINESIZE:
i can't find documentation for these, what meaning do users expect?