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Re: RISC-V glibc Port v1
- From: Palmer Dabbelt <palmer at dabbelt dot com>
- To: joseph at codesourcery dot com
- Cc: libc-alpha at sourceware dot org
- Cc: Andrew Waterman <andrew at sifive dot com>
- Cc: patches at groups dot riscv dot org
- Cc: Darius Rad <darius at bluespec dot com>
- Date: Wed, 14 Jun 2017 13:33:50 -0700 (PDT)
- Subject: Re: RISC-V glibc Port v1
- Authentication-results: sourceware.org; auth=none
On Wed, 14 Jun 2017 13:14:22 PDT (-0700), joseph@codesourcery.com wrote:
> General observations, to be addressed globally for the patch series:
>
> * All new files should have a descriptive comment on their first line,
> before the copyright notice.
>
> * All copyright notices should use a single range of years, <year>-2017,
> assuming the first year is no earlier than 1990.
>
> * No "Contributed by" notices in any new files.
>
> * All license notices should have a URL, not an old FSF postal address.
OK, I'll change those for the v2.
> * Please include changes to build-many-glibcs.py to make it build glibc
> for all the supported ABI variants (I think from this patch series there
> are six different mutually incompatible ABI variants supported?). Make
> sure that, if you use your patched Linux kernel sources, all six variants,
> as built with build-many-glibcs.py, both build cleanly and produce clean
> results for the compilation parts of the glibc testsuite, with both GCC 7
> and current GCC trunk. (For variations that are instruction set variants
> rather than ABI variants, it's at your discretion whether it's useful to
> build glibc for such variants as well; that depends on whether doing so
> covers significant extra code in glibc that would not otherwise be built.)
RISC-V is a modular ISA, and as such there are many ISA variants. The actual
number is the Cartesian product of:
* RV32I, RV64I: base ISA, which defines the length of GP registers (which we
call XLEN).
* M or no-M: multiply support or not.
* A or no-A: atomic instruction support or not.
* none, F, or D: the floating-point format supported, either none, single or
double.
* C or no-C: compressed instructions support or not.
In addition to the ISA variants, we support soft, single-hard, and double-hard
float ABIs on any ISA that includes the required floating-point registers.
In order to avoid building this huge number of ISA variants we only actively
support and test the following configurations
march=rv32imac/mabi=ilp32
march=rv32imafdc/mabi=ilp32d
march=rv64imac/mabi=lp64
march=rv64imafdc/mabi=lp64d
for glibc. I'll add those to the build script, and verify they build with the
relevant GCC versions.
> * Also include details of the full testsuite results, including execution
> tests (which build-many-glibcs.py can't run), for all ABI variants again,
> in the next submission of the port.
We've just been running the GCC test suite. I'll take a shot at running the
glibc test suite as well.
Thanks!