This is the mail archive of the
mailing list for the glibc project.
Re: [PATCH][BZ #19490] Add unwind descriptors to pthread_spin_init, etc. on i386
- From: Torvald Riegel <triegel at redhat dot com>
- To: Szabolcs Nagy <szabolcs dot nagy at arm dot com>
- Cc: Paul Pluzhnikov <ppluzhnikov at google dot com>, GLIBC Devel <libc-alpha at sourceware dot org>, nd at arm dot com
- Date: Mon, 01 Feb 2016 13:31:56 +0100
- Subject: Re: [PATCH][BZ #19490] Add unwind descriptors to pthread_spin_init, etc. on i386
- Authentication-results: sourceware.org; auth=none
- References: <CALoOobPJLwc+iSG+w-2YqqiL6=iAL-ZPiS5iKtmdDmJTR9Fp6g at mail dot gmail dot com> <1453727190 dot 4592 dot 91 dot camel at localhost dot localdomain> <CALoOobP6+GGSCMwiXsgQY4zLCXKpSsOA=4fOdB+J9q20bmtWOw at mail dot gmail dot com> <1454326614 dot 4592 dot 293 dot camel at localhost dot localdomain> <56AF49AD dot 5020108 at arm dot com>
On Mon, 2016-02-01 at 12:03 +0000, Szabolcs Nagy wrote:
> On 01/02/16 11:36, Torvald Riegel wrote:
> > On Sun, 2016-01-31 at 15:09 -0800, Paul Pluzhnikov wrote:
> >> On Mon, Jan 25, 2016 at 5:06 AM, Torvald Riegel <firstname.lastname@example.org> wrote:
> >>> For the spinlocks, I'd really prefer if we could just remove the asm
> >>> files. The generic implementation should basically produce the same
> >>> code; if not, we should try to fix that instead of keeping the asm
> >>> files.
> >> Using gcc-4.8.4 (4.8.4-2ubuntu1~14.04):
> >> $ objdump -d nptl/pthread_spin_unlock.o
> >> nptl/pthread_spin_unlock.o: file format elf32-i386
> >> Disassembly of section .text:
> >> 00000000 <pthread_spin_unlock>:
> >> 0: f0 83 0c 24 00 lock orl $0x0,(%esp)
> >> 5: 8b 44 24 04 mov 0x4(%esp),%eax
> >> 9: c7 00 00 00 00 00 movl $0x0,(%eax)
> >> f: 31 c0 xor %eax,%eax
> >> 11: c3 ret
> >> This isn't quite the same as sysdeps/i386/nptl/pthread_spin_unlock.S
> > This is because nptl/pthread_spin_unlock.c still issues a full barrier.
> > If this is changed to an atomic_store_release, one gets this on x86_64:
> > 0000000000000000 <pthread_spin_unlock>:
> > 0: c7 07 00 00 00 00 movl $0x0,(%rdi)
> > 6: 31 c0 xor %eax,%eax
> > 8: c3
> > Perhaps now is a good time to finally get this done. Most archs are
> > already using acquire semantics, IIRC. I think aarch64 and arm are the
> > only major ones that happen to use the current generic unlock with full
> > barrier -- but they only use acquire MO on unlock, so there's really no
> > consistent pattern that would justify this.
> i think mb(); store(); is actually *weaker* than store_release();
If that's indeed the case in the context of the C11 memory model, this
is a bug. But I would be surprised if that's the case. It would also
be a bug if the atomic_full_barrier implementation we have currently is
actually not implementing a C11 seq_cst barrier.
Also cross-check against the mappings here, which I trust to be correct:
> and thus on some hw it might be a bit faster, but i'm not against
> changing to store_release (that's one step closer to posix semantics).
In the context of the memory model used in glibc, store_release is
weaker than a atomic_full_barrier (which is supposed to be at least as
strong as a C11 seq_cst fence).
> (full barrier is weaker here because store_release() has to
> prevent reordering wrt load_acquire in *both* directions, so
> it may be implemented by the hw like mb(); store(); mb();
> although that's not the most efficient implementation..)
I'm not an expert on the ARM memory model, but I believe your assumption
that the semantics we require for atomic_store_release has to prevent
reordering in both directions on ARM is wrong. Even a compiler can
often move stuff from after to before a store_release; the release MO
guarantee is, simplified, something like "if something was before the
release MO on the release side, it will not appear on the observer's
side as if after the release, provided the observer used an acquire load
to observe the release store".
> > Note that there's an ongoing debate about whether POSIX requires
> > pthread_spin_unlock to be a full barrier, whether it should or should
> the current unlock is not enough for posix if trylock is
> acquire MO:
> if (trylock(l2))...
> if (trylock(l1))...
> with one sided barrier, both trylock can fail to grab
> the lock (the loads are not guaranteed to happen after
> the stores) which is not seq cst, this does not happen
> with release MO unlock.
No. If unlock is a release MO store, and trylock is an acquire load,
then both trylocks can fail and both trylock's can succeed. Your
example is similar to Dekker synchronization, and Dekker synchronization
is never guaranteed to produce a winner, and release/acquire are not
sufficient to implement it. I suggest using the cppmem tool to play
around with it and have a look at the possible executions.
If unlock is a seq_cst store and trylock is a seq_cst acquire, this
Dekker implementation would work except that POSIX doesn't guarantee
"synchronizes memory" for a call that fails (so the trylock isn't
sufficient, and you have to assume something like that it can fail
If unlock were an at-least-release MO fence followed by a relaxed MO
store to the lock followed by a seq_cst fence, this example would work.
But this shows, in turn, that (a) "synchronizes memory" can be costly to
implement and (b) POSIX shouldn't try to support hacks that emulate
proper atomics (ie, trylock in the example above).