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Re: [PATCHv2] powerpc: Spinlock optimization and cleanup
- From: Steven Munroe <munroesj at linux dot vnet dot ibm dot com>
- To: Szabolcs Nagy <szabolcs dot nagy at arm dot com>
- Cc: "Paul E. Murphy" <murphyp at linux dot vnet dot ibm dot com>, "libc-alpha at sourceware dot org" <libc-alpha at sourceware dot org>, "triegel at redhat dot com" <triegel at redhat dot com>, "rth at twiddle dot net" <rth at twiddle dot net>, Tulio Magno Quites Machado Filho <tuliom at linux dot vnet dot ibm dot com>, Adhemerval Zanella <adhemerval dot zanella at linaro dot org>, Steve Munroe <sjmunroe at us dot ibm dot com>
- Date: Thu, 01 Oct 2015 10:27:43 -0500
- Subject: Re: [PATCHv2] powerpc: Spinlock optimization and cleanup
- Authentication-results: sourceware.org; auth=none
- References: <560C0DA6 dot 5060409 at linux dot vnet dot ibm dot com> <560CFA64 dot 2030205 at arm dot com>
- Reply-to: munroesj at linux dot vnet dot ibm dot com
On Thu, 2015-10-01 at 10:18 +0100, Szabolcs Nagy wrote:
> On 30/09/15 17:28, Paul E. Murphy wrote:
> >
> > ---8<---
> > This patch optimizes powerpc spinlock implementation by:
> >
> ...
>
> The glibc pthread spinlock semantics is weaker than what
> posix requires, I'm wondering if this is expected to stay
> or glibc might want to switch to stronger semantics.
>
Since when? Include the text the requires this?
> is it worthwhile to add optimized asm with weak semantics
> for other targets that currently use the generic c code?
>
> (the issue is that for correct pthread_spin_trylock behavior
> the lock should be seqcst instead of acquire and the unlock
> should be release instead of barrier+store otherwise trylock
> can spuriously report locked state).
>
Paul patch already changes pthread_spin_unlock to atomic_store_release,
which will generate lwsync/stw.
But I don't think anyone wants or need pthread_spin_lock to be seqcst.
Also as the acquire sequence used in Paul patch is a full "import
barrier", it is sufficient for the critical region.
Read PowerISA-2.07B BookII Appendix B Programming Examples for Shared
Storage, Section B.2.1 Lock Acquisition and Import Barriers.
Which specifically say that a hwsync is not required if the acquire
import barrier is used. And this sequence will perform better.