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Re: [PATCH][RFC] Fix SPARC atomic_write_barrier.
- From: David Miller <davem at davemloft dot net>
- To: triegel at redhat dot com
- Cc: libc-alpha at sourceware dot org
- Date: Thu, 30 Oct 2014 19:08:16 -0400 (EDT)
- Subject: Re: [PATCH][RFC] Fix SPARC atomic_write_barrier.
- Authentication-results: sourceware.org; auth=none
- References: <1414703220 dot 10085 dot 209 dot camel at triegel dot csb>
From: Torvald Riegel <triegel@redhat.com>
Date: Thu, 30 Oct 2014 22:07:00 +0100
> This patch changes SPARC write barriers to be just release barriers. I
> haven't tested this, so this is based on my understanding of the SPARC
> memory model (TSO).
The sparc memory model is variable.
It can be TSO, PSO, or RMO.
It is controlled by a bit in the processor state register, and not
all cpus support all memory models.
Linux happens to run all threads in TSO currently, but this is not
something GLIBC or any userland code should really depend upon.
So we should use whatever memory barriers are necessary in the least
strict memory model possible, which is RMO.