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Re: Transition to C11 atomics and memory model

On Sun, 14 Sep 2014, Torvald Riegel wrote:

> 1) Add new C11-like atomics.  If GCC supports them on this architecture,
> use GCC's atomic builtins.  Make them fall back to the existing atomics
> otherwise.  Attached is a small patch that illustrates this.

I'm not clear on how you propose to determine whether to define 

The obvious approach of testing __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 (etc.), 
together with making sure the GCC version is at least 4.7, runs into 
architecture-specific problems:

* While the builtins are available in 4.7, on some architectures they may 
be suboptimal before a later version (see the MIPS code preferring to use 
them only for 4.8 and later, but using them for 4.7 in the MIPS16 case; 
generally this applies if the GCC support was originally implemented for 
__sync_*, with its stronger barrier requirements, but the architecture 
does support specifying the required memory ordering more precisely, but 
the GCC support for that was added later).

* In some cases those macros are defined by GCC even though the operations 
are out of line in libgcc.  On PA the HAVE_sync_compare_and_swap* macros 
are defined in pa-linux.h to cause __GCC_HAVE_SYNC_COMPARE_AND_SWAP_* to 
be predefined; for Tile GCC has special target-specific code to define 
__GCC_HAVE_SYNC_COMPARE_AND_SWAP_*.  Do we believe such out-of-line libgcc 
versions will work in glibc, and is it preferable to use them or inline 
asm?  (My guess is that they might work except for cases such as the 
64-bit ARM atomics with references to libc interfaces.)

So if you have a default based on those macros, you'd need to allow for 
architectures overriding it.

Joseph S. Myers

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