This is the mail archive of the mailing list for the glibc project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[PATCH] Fix ARM NAN fraction bits

Current ARM soft-float implementation is violating the RTABI
f) Section

When not otherwise specified by IEEE 754, the result on an invalid operation
should be the quiet NaN bit pattern with only the most significant bit of
the significand set, and all other significand bits zero. 

This patch fixes it by setting _FP_NANFRAC_* to zero.

Ran make check test with –mfloat-abi=soft. No regression.

OK to checkin?

2014-02-27  Joey Ye  <>
* sysdeps/arm/soft-fp/sfp-machine.h 
  Set to zero.

diff --git a/sysdeps/arm/soft-fp/sfp-machine.h
index 52a08b5..32697fe 100644
--- a/sysdeps/arm/soft-fp/sfp-machine.h
+++ b/sysdeps/arm/soft-fp/sfp-machine.h
@@ -21,9 +21,9 @@
#define _FP_DIV_MEAT_D(R,X,Y)          _FP_DIV_MEAT_2_udiv(D,R,X,Y)
#define _FP_DIV_MEAT_Q(R,X,Y)          _FP_DIV_MEAT_4_udiv(Q,R,X,Y)

-#define _FP_NANFRAC_S                          ((_FP_QNANBIT_S << 1) - 1)
-#define _FP_NANFRAC_D                         ((_FP_QNANBIT_D << 1) - 1),
-#define _FP_NANFRAC_Q                         ((_FP_QNANBIT_Q << 1) - 1),
-1, -1, -1
+#define _FP_NANFRAC_S                         0
+#define _FP_NANFRAC_D                        0, 0
+#define _FP_NANFRAC_Q                        0, 0, 0, 0
#define _FP_NANSIGN_S                           0
#define _FP_NANSIGN_D                          0
#define _FP_NANSIGN_Q                          0

Attachment: nan_frac_zero_glibc-0214.patch
Description: Binary data

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]