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[PATCH] Optimized sparc ceil{,f} and rint{,f} routines.
- From: David Miller <davem at davemloft dot net>
- To: libc-alpha at sourceware dot org
- Date: Mon, 27 Feb 2012 17:59:22 -0500 (EST)
- Subject: [PATCH] Optimized sparc ceil{,f} and rint{,f} routines.
I tend to pick away at some other libm routines in the near future
to optimize them for sparc we well.
Committed to master.
* sysdeps/sparc/sparc32/sparcv9/fpu/s_ceil.S: New file.
* sysdeps/sparc/sparc32/sparcv9/fpu/s_ceilf.S: New file.
* sysdeps/sparc/sparc32/sparcv9/fpu/s_rint.S: New file.
* sysdeps/sparc/sparc32/sparcv9/fpu/s_rintf.S: New file.
* sysdeps/sparc/sparc64/fpu/s_ceil.S: New file.
* sysdeps/sparc/sparc64/fpu/s_ceilf.S: New file.
* sysdeps/sparc/sparc64/fpu/s_rint.S: New file.
* sysdeps/sparc/sparc64/fpu/s_rintf.S: New file.
---
ChangeLog | 9 +++
sysdeps/sparc/sparc32/sparcv9/fpu/s_ceil.S | 88 +++++++++++++++++++++++++++
sysdeps/sparc/sparc32/sparcv9/fpu/s_ceilf.S | 84 +++++++++++++++++++++++++
sysdeps/sparc/sparc32/sparcv9/fpu/s_rint.S | 65 ++++++++++++++++++++
sysdeps/sparc/sparc32/sparcv9/fpu/s_rintf.S | 60 ++++++++++++++++++
sysdeps/sparc/sparc64/fpu/s_ceil.S | 84 +++++++++++++++++++++++++
sysdeps/sparc/sparc64/fpu/s_ceilf.S | 82 +++++++++++++++++++++++++
sysdeps/sparc/sparc64/fpu/s_rint.S | 58 ++++++++++++++++++
sysdeps/sparc/sparc64/fpu/s_rintf.S | 57 +++++++++++++++++
9 files changed, 587 insertions(+), 0 deletions(-)
create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/s_ceil.S
create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/s_ceilf.S
create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/s_rint.S
create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/s_rintf.S
create mode 100644 sysdeps/sparc/sparc64/fpu/s_ceil.S
create mode 100644 sysdeps/sparc/sparc64/fpu/s_ceilf.S
create mode 100644 sysdeps/sparc/sparc64/fpu/s_rint.S
create mode 100644 sysdeps/sparc/sparc64/fpu/s_rintf.S
diff --git a/ChangeLog b/ChangeLog
index 5ac7ec7..c41eec3 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,5 +1,14 @@
2012-02-27 David S. Miller <davem@davemloft.net>
+ * sysdeps/sparc/sparc32/sparcv9/fpu/s_ceil.S: New file.
+ * sysdeps/sparc/sparc32/sparcv9/fpu/s_ceilf.S: New file.
+ * sysdeps/sparc/sparc32/sparcv9/fpu/s_rint.S: New file.
+ * sysdeps/sparc/sparc32/sparcv9/fpu/s_rintf.S: New file.
+ * sysdeps/sparc/sparc64/fpu/s_ceil.S: New file.
+ * sysdeps/sparc/sparc64/fpu/s_ceilf.S: New file.
+ * sysdeps/sparc/sparc64/fpu/s_rint.S: New file.
+ * sysdeps/sparc/sparc64/fpu/s_rintf.S: New file.
+
* sysdeps/ieee754/ldbl-128/s_nearbyintl.c (__nearbyintl): Do not
manipulate bits before adding and subtracting TWO112[sx].
* sysdeps/ieee754/ldbl-128/s_rintl.c (__rintl): Likewise.
diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/s_ceil.S b/sysdeps/sparc/sparc32/sparcv9/fpu/s_ceil.S
new file mode 100644
index 0000000..7364f82
--- /dev/null
+++ b/sysdeps/sparc/sparc32/sparcv9/fpu/s_ceil.S
@@ -0,0 +1,88 @@
+/* ceil function, sparc32 v9 version.
+ Copyright (C) 2012 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+ Contributed by David S. Miller <davem@davemloft.net>, 2012.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include <sysdep.h>
+
+ /* Since changing the rounding mode is extremely expensive, we
+ * try to round up using a method that is rounding mode
+ * agnostic.
+ *
+ * We add then subtract (or subtract than add if the initial
+ * value was negative) 2**23 to the value, then subtract it
+ * back out.
+ *
+ * This will clear out the fractional portion of the value.
+ * One of two things will happen for non-whole initial values.
+ * Either the rounding mode will round it up, or it will be
+ * rounded down. If the value started out whole, it will be
+ * equal after the addition and subtraction. This means we
+ * can accurately detect with one test whether we need to add
+ * another 1.0 to round it up properly.
+ *
+ * We pop constants into the FPU registers using the incoming
+ * argument stack slots, since this avoid having to use any PIC
+ * references. We also thus avoid having to allocate a register
+ * window.
+ *
+ * VIS instructions are used to facilitate the formation of
+ * easier constants, and the propagation of the sign bit.
+ */
+
+#define TWO_FIFTYTWO 0x43300000 /* 2**52 */
+#define ONE_DOT_ZERO 0x3ff00000 /* 1.0 */
+
+#define ZERO %f10 /* 0.0 */
+#define SIGN_BIT %f12 /* -0.0 */
+
+ENTRY (__ceil)
+ sethi %hi(TWO_FIFTYTWO), %o2
+ sllx %o0, 32, %o0
+ sethi %hi(ONE_DOT_ZERO), %o3
+ or %o0, %o1, %o0
+ stx %o0, [%sp + 72]
+ sllx %o2, 32, %o2
+ fzero ZERO
+ sllx %o3, 32, %o3
+
+ ldd [%sp + 72], %f0
+ fnegd ZERO, SIGN_BIT
+
+ stx %o2, [%sp + 72]
+ fabsd %f0, %f14
+
+ ldd [%sp + 72], %f16
+ fcmpd %fcc3, %f14, %f16
+
+ fmovduge %fcc3, ZERO, %f16
+ fand %f0, SIGN_BIT, SIGN_BIT
+
+ for %f16, SIGN_BIT, %f16
+ faddd %f0, %f16, %f18
+ fsubd %f18, %f16, %f18
+ fcmpd %fcc2, %f18, %f0
+ stx %o3, [%fp + 72]
+
+ ldd [%fp + 72], %f20
+ fmovduge %fcc2, ZERO, %f20
+ faddd %f18, %f20, %f0
+ fabsd %f0, %f0
+ retl
+ for %f0, SIGN_BIT, %f0
+END (__ceil)
+weak_alias (__ceil, ceil)
diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/s_ceilf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/s_ceilf.S
new file mode 100644
index 0000000..fbc6faa
--- /dev/null
+++ b/sysdeps/sparc/sparc32/sparcv9/fpu/s_ceilf.S
@@ -0,0 +1,84 @@
+/* Float ceil function, sparc32 v9 version.
+ Copyright (C) 2012 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+ Contributed by David S. Miller <davem@davemloft.net>, 2012.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include <sysdep.h>
+
+ /* Since changing the rounding mode is extremely expensive, we
+ * try to round up using a method that is rounding mode
+ * agnostic.
+ *
+ * We add then subtract (or subtract than add if the initial
+ * value was negative) 2**23 to the value, then subtract it
+ * back out.
+ *
+ * This will clear out the fractional portion of the value.
+ * One of two things will happen for non-whole initial values.
+ * Either the rounding mode will round it up, or it will be
+ * rounded down. If the value started out whole, it will be
+ * equal after the addition and subtraction. This means we
+ * can accurately detect with one test whether we need to add
+ * another 1.0 to round it up properly.
+ *
+ * We pop constants into the FPU registers using the incoming
+ * argument stack slots, since this avoid having to use any PIC
+ * references. We also thus avoid having to allocate a register
+ * window.
+ *
+ * VIS instructions are used to facilitate the formation of
+ * easier constants, and the propagation of the sign bit.
+ */
+
+#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */
+#define ONE_DOT_ZERO 0x3f800000 /* 1.0 */
+
+#define ZERO %f10 /* 0.0 */
+#define SIGN_BIT %f12 /* -0.0 */
+
+ENTRY (__ceilf)
+ st %o0, [%sp + 68]
+ sethi %hi(TWO_TWENTYTHREE), %o2
+ sethi %hi(ONE_DOT_ZERO), %o3
+ fzeros ZERO
+
+ ld [%sp + 68], %f0
+ fnegs ZERO, SIGN_BIT
+
+ st %o2, [%sp + 68]
+ fabss %f0, %f14
+
+ ld [%sp + 68], %f16
+ fcmps %fcc3, %f14, %f16
+
+ fmovsuge %fcc3, ZERO, %f16
+ fands %f0, SIGN_BIT, SIGN_BIT
+
+ fors %f16, SIGN_BIT, %f16
+ fadds %f0, %f16, %f1
+ fsubs %f1, %f16, %f1
+ fcmps %fcc2, %f1, %f0
+ st %o3, [%fp + 68]
+
+ ld [%fp + 68], %f9
+ fmovsuge %fcc2, ZERO, %f9
+ fadds %f1, %f9, %f0
+ fabss %f0, %f0
+ retl
+ fors %f0, SIGN_BIT, %f0
+END (__ceilf)
+weak_alias (__ceilf, ceilf)
diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/s_rint.S b/sysdeps/sparc/sparc32/sparcv9/fpu/s_rint.S
new file mode 100644
index 0000000..8cae9b8
--- /dev/null
+++ b/sysdeps/sparc/sparc32/sparcv9/fpu/s_rint.S
@@ -0,0 +1,65 @@
+/* Round float to int floating-point values, sparc32 v9 version.
+ Copyright (C) 2012 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+ Contributed by David S. Miller <davem@davemloft.net>, 2012.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include <sysdep.h>
+
+ /* We pop constants into the FPU registers using the incoming
+ * argument stack slots, since this avoid having to use any PIC
+ * references. We also thus avoid having to allocate a register
+ * window.
+ *
+ * VIS instructions are used to facilitate the formation of
+ * easier constants, and the propagation of the sign bit.
+ */
+
+#define TWO_FIFTYTWO 0x43300000 /* 2**52 */
+
+#define ZERO %f10 /* 0.0 */
+#define SIGN_BIT %f12 /* -0.0 */
+
+ENTRY (__rint)
+ sethi %hi(TWO_FIFTYTWO), %o2
+ sllx %o0, 32, %o0
+
+ or %o0, %o1, %o0
+ fzero ZERO
+
+ stx %o0, [%sp + 72]
+ sllx %o2, 32, %o2
+ fnegd ZERO, SIGN_BIT
+
+ ldd [%sp + 72], %f0
+
+ stx %o2, [%sp + 72]
+ fabsd %f0, %f14
+
+ ldd [%sp + 72], %f16
+ fcmpd %fcc3, %f14, %f16
+
+ fmovduge %fcc3, ZERO, %f16
+ fand %f0, SIGN_BIT, SIGN_BIT
+
+ for %f16, SIGN_BIT, %f16
+ faddd %f0, %f16, %f6
+ fsubd %f6, %f16, %f0
+ fabsd %f0, %f0
+ retl
+ for %f0, SIGN_BIT, %f0
+END (__rint)
+weak_alias (__rint, rint)
diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/s_rintf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/s_rintf.S
new file mode 100644
index 0000000..2e67fa7
--- /dev/null
+++ b/sysdeps/sparc/sparc32/sparcv9/fpu/s_rintf.S
@@ -0,0 +1,60 @@
+/* Round float to int floating-point values, sparc32 v9 version.
+ Copyright (C) 2012 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+ Contributed by David S. Miller <davem@davemloft.net>, 2012.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include <sysdep.h>
+
+ /* We pop constants into the FPU registers using the incoming
+ * argument stack slots, since this avoid having to use any PIC
+ * references. We also thus avoid having to allocate a register
+ * window.
+ *
+ * VIS instructions are used to facilitate the formation of
+ * easier constants, and the propagation of the sign bit.
+ */
+
+#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */
+
+#define ZERO %f10 /* 0.0 */
+#define SIGN_BIT %f12 /* -0.0 */
+
+ENTRY (__rintf)
+ st %o0, [%sp + 68]
+ sethi %hi(TWO_TWENTYTHREE), %o2
+ fzeros ZERO
+
+ ld [%sp + 68], %f1
+ fnegs ZERO, SIGN_BIT
+
+ st %o2, [%sp + 68]
+ fabss %f1, %f14
+
+ ld [%sp + 68], %f16
+ fcmps %fcc3, %f14, %f16
+
+ fmovsuge %fcc3, ZERO, %f16
+ fands %f1, SIGN_BIT, SIGN_BIT
+
+ fors %f16, SIGN_BIT, %f16
+ fadds %f1, %f16, %f5
+ fsubs %f5, %f16, %f0
+ fabss %f0, %f0
+ retl
+ fors %f0, SIGN_BIT, %f0
+END (__rintf)
+weak_alias (__rintf, rintf)
diff --git a/sysdeps/sparc/sparc64/fpu/s_ceil.S b/sysdeps/sparc/sparc64/fpu/s_ceil.S
new file mode 100644
index 0000000..7e9bfef
--- /dev/null
+++ b/sysdeps/sparc/sparc64/fpu/s_ceil.S
@@ -0,0 +1,84 @@
+/* ceil function, sparc64 version.
+ Copyright (C) 2012 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+ Contributed by David S. Miller <davem@davemloft.net>, 2012.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include <sysdep.h>
+
+ /* Since changing the rounding mode is extremely expensive, we
+ * try to round up using a method that is rounding mode
+ * agnostic.
+ *
+ * We add then subtract (or subtract than add if the initial
+ * value was negative) 2**23 to the value, then subtract it
+ * back out.
+ *
+ * This will clear out the fractional portion of the value.
+ * One of two things will happen for non-whole initial values.
+ * Either the rounding mode will round it up, or it will be
+ * rounded down. If the value started out whole, it will be
+ * equal after the addition and subtraction. This means we
+ * can accurately detect with one test whether we need to add
+ * another 1.0 to round it up properly.
+ *
+ * We pop constants into the FPU registers using the incoming
+ * argument stack slots, since this avoid having to use any PIC
+ * references. We also thus avoid having to allocate a register
+ * window.
+ *
+ * VIS instructions are used to facilitate the formation of
+ * easier constants, and the propagation of the sign bit.
+ */
+
+#define TWO_FIFTYTWO 0x43300000 /* 2**52 */
+#define ONE_DOT_ZERO 0x3ff00000 /* 1.0 */
+
+#define ZERO %f10 /* 0.0 */
+#define SIGN_BIT %f12 /* -0.0 */
+
+ENTRY (__ceil)
+ sethi %hi(TWO_FIFTYTWO), %o2
+ sethi %hi(ONE_DOT_ZERO), %o3
+ fzero ZERO
+
+ sllx %o2, 32, %o2
+ fnegd ZERO, SIGN_BIT
+
+ sllx %o3, 32, %o3
+ stx %o2, [%sp + STACK_BIAS + 128]
+ fabsd %f0, %f14
+
+ ldd [%sp + STACK_BIAS + 128], %f16
+ fcmpd %fcc3, %f14, %f16
+
+ fmovduge %fcc3, ZERO, %f16
+ fand %f0, SIGN_BIT, SIGN_BIT
+
+ for %f16, SIGN_BIT, %f16
+ faddd %f0, %f16, %f18
+ fsubd %f18, %f16, %f18
+ fcmpd %fcc2, %f18, %f0
+ stx %o3, [%fp + STACK_BIAS + 128]
+
+ ldd [%fp + STACK_BIAS + 128], %f20
+ fmovduge %fcc2, ZERO, %f20
+ faddd %f18, %f20, %f0
+ fabsd %f0, %f0
+ retl
+ for %f0, SIGN_BIT, %f0
+END (__ceil)
+weak_alias (__ceil, ceil)
diff --git a/sysdeps/sparc/sparc64/fpu/s_ceilf.S b/sysdeps/sparc/sparc64/fpu/s_ceilf.S
new file mode 100644
index 0000000..1ae7f7a
--- /dev/null
+++ b/sysdeps/sparc/sparc64/fpu/s_ceilf.S
@@ -0,0 +1,82 @@
+/* Float ceil function, sparc64 version.
+ Copyright (C) 2012 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+ Contributed by David S. Miller <davem@davemloft.net>, 2012.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include <sysdep.h>
+
+ /* Since changing the rounding mode is extremely expensive, we
+ * try to round up using a method that is rounding mode
+ * agnostic.
+ *
+ * We add then subtract (or subtract than add if the initial
+ * value was negative) 2**23 to the value, then subtract it
+ * back out.
+ *
+ * This will clear out the fractional portion of the value.
+ * One of two things will happen for non-whole initial values.
+ * Either the rounding mode will round it up, or it will be
+ * rounded down. If the value started out whole, it will be
+ * equal after the addition and subtraction. This means we
+ * can accurately detect with one test whether we need to add
+ * another 1.0 to round it up properly.
+ *
+ * We pop constants into the FPU registers using the incoming
+ * argument stack slots, since this avoid having to use any PIC
+ * references. We also thus avoid having to allocate a register
+ * window.
+ *
+ * VIS instructions are used to facilitate the formation of
+ * easier constants, and the propagation of the sign bit.
+ */
+
+#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */
+#define ONE_DOT_ZERO 0x3f800000 /* 1.0 */
+
+#define ZERO %f10 /* 0.0 */
+#define SIGN_BIT %f12 /* -0.0 */
+
+ENTRY (__ceilf)
+ sethi %hi(TWO_TWENTYTHREE), %o2
+ sethi %hi(ONE_DOT_ZERO), %o3
+ fzeros ZERO
+
+ fnegs ZERO, SIGN_BIT
+
+ st %o2, [%sp + STACK_BIAS + 128]
+ fabss %f1, %f14
+
+ ld [%sp + STACK_BIAS + 128], %f16
+ fcmps %fcc3, %f14, %f16
+
+ fmovsuge %fcc3, ZERO, %f16
+ fands %f1, SIGN_BIT, SIGN_BIT
+
+ fors %f16, SIGN_BIT, %f16
+ fadds %f1, %f16, %f5
+ fsubs %f5, %f16, %f5
+ fcmps %fcc2, %f5, %f1
+ st %o3, [%fp + STACK_BIAS + 128]
+
+ ld [%fp + STACK_BIAS + 128], %f9
+ fmovsuge %fcc2, ZERO, %f9
+ fadds %f5, %f9, %f0
+ fabss %f0, %f0
+ retl
+ fors %f0, SIGN_BIT, %f0
+END (__ceilf)
+weak_alias (__ceilf, ceilf)
diff --git a/sysdeps/sparc/sparc64/fpu/s_rint.S b/sysdeps/sparc/sparc64/fpu/s_rint.S
new file mode 100644
index 0000000..38b6135
--- /dev/null
+++ b/sysdeps/sparc/sparc64/fpu/s_rint.S
@@ -0,0 +1,58 @@
+/* Round float to int floating-point values, sparc64 version.
+ Copyright (C) 2012 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+ Contributed by David S. Miller <davem@davemloft.net>, 2012.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include <sysdep.h>
+
+ /* We pop constants into the FPU registers using the incoming
+ * argument stack slots, since this avoid having to use any PIC
+ * references. We also thus avoid having to allocate a register
+ * window.
+ *
+ * VIS instructions are used to facilitate the formation of
+ * easier constants, and the propagation of the sign bit.
+ */
+
+#define TWO_FIFTYTWO 0x43300000 /* 2**52 */
+
+#define ZERO %f10 /* 0.0 */
+#define SIGN_BIT %f12 /* -0.0 */
+
+ENTRY (__rint)
+ sethi %hi(TWO_FIFTYTWO), %o2
+ sllx %o2, 32, %o2
+ fzero ZERO
+
+ fnegd ZERO, SIGN_BIT
+ stx %o2, [%sp + STACK_BIAS + 128]
+ fabsd %f0, %f14
+
+ ldd [%sp + STACK_BIAS + 128], %f16
+ fcmpd %fcc3, %f14, %f16
+
+ fmovduge %fcc3, ZERO, %f16
+ fand %f0, SIGN_BIT, SIGN_BIT
+
+ for %f16, SIGN_BIT, %f16
+ faddd %f0, %f16, %f6
+ fsubd %f6, %f16, %f0
+ fabsd %f0, %f0
+ retl
+ for %f0, SIGN_BIT, %f0
+END (__rint)
+weak_alias (__rint, rint)
diff --git a/sysdeps/sparc/sparc64/fpu/s_rintf.S b/sysdeps/sparc/sparc64/fpu/s_rintf.S
new file mode 100644
index 0000000..42fda3f
--- /dev/null
+++ b/sysdeps/sparc/sparc64/fpu/s_rintf.S
@@ -0,0 +1,57 @@
+/* Round float to int floating-point values, sparc64 version.
+ Copyright (C) 2012 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+ Contributed by David S. Miller <davem@davemloft.net>, 2012.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+#include <sysdep.h>
+
+ /* We pop constants into the FPU registers using the incoming
+ * argument stack slots, since this avoid having to use any PIC
+ * references. We also thus avoid having to allocate a register
+ * window.
+ *
+ * VIS instructions are used to facilitate the formation of
+ * easier constants, and the propagation of the sign bit.
+ */
+
+#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */
+
+#define ZERO %f10 /* 0.0 */
+#define SIGN_BIT %f12 /* -0.0 */
+
+ENTRY (__rintf)
+ sethi %hi(TWO_TWENTYTHREE), %o2
+ fzeros ZERO
+
+ fnegs ZERO, SIGN_BIT
+ st %o2, [%sp + STACK_BIAS + 128]
+ fabss %f1, %f14
+
+ ld [%sp + STACK_BIAS + 128], %f16
+ fcmps %fcc3, %f14, %f16
+
+ fmovsuge %fcc3, ZERO, %f16
+ fands %f1, SIGN_BIT, SIGN_BIT
+
+ fors %f16, SIGN_BIT, %f16
+ fadds %f1, %f16, %f5
+ fsubs %f5, %f16, %f0
+ fabss %f0, %f0
+ retl
+ fors %f0, SIGN_BIT, %f0
+END (__rintf)
+weak_alias (__rintf, rintf)
--
1.7.6.401.g6a319