[PATCH] improved isnan[f] implementations for power5, powe6, and power6x

[Steven Munroe <munroesj at linux dot vnet dot ibm dot com>]

The patch for BZ #5768 fixed the isnan (and isnanf) implementation with
a general solution that is correct and reasonably efficient for existing
(POWER4 and earlier) implementations. 

However starting with POWER5 a more aggressive pipeline structure means
that the Move from FPSCR (and related instructions) are completion
serializing (delayed until the FPU pipelines are empty). This implies
that the technique of copying the FPR to a GRP (via a in store union)
and bit masking to detect NaN can be a better performer (than the base
implementation using mffs/mtfsf).

This is only true if the GPR load hits the store queue bypass and avoids
the full load-hit-store reject. This requires insertion of nops to
insure that the store float [double|single] and load [word|double] are
dispatched in different cycles (different dispatch groups). This is not
supported in the generic isnan.c implementation.

The attached patch provides optimal isnan[f] implementations for
--with-cpu=[power5|power6|power6x].

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