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Re: [PATCH] hp-timing for ppc32/64
- From: Steve Munroe <sjmunroe at us dot ibm dot com>
- To: Kumar Gala <kumar dot gala at freescale dot com>
- Cc: "Benjamin Herrenschmidt" <benh at kernel dot crashing dot org>, libc-alpha at sources dot redhat dot com
- Date: Mon, 17 Oct 2005 20:24:56 -0500
- Subject: Re: [PATCH] hp-timing for ppc32/64
Kumar Gala <kumar.gala@freescale.com> wrote on 10/17/2005 05:40:19 PM:
> >> Note that some CPUs like the 970 can have an externally clocked
> >> timebase. Apple uses this feature to make the CPU immune to bus/cpu
> >> frequency slewing, they use a 33Mhz clock for that.
> >>
> >>
> > The 970 does not implement a alternate timebase. So for 970 the
> > timebase
> >
> > is the highest frequency counter available.
> > It seems that Apple choose 33MHz to meet the minimum (slowest)CPU-
> > clock
> > /
> > 32 timebase. But that was their choice. The IBM hardware seems to be
> > holding to the CPU_clock / 8 timebase (including 970 based JS20).
>
> One could argue that the performance monitors could be used as a
> cycle counter on 970 :)
>
The number and function of performance monitor registers vary randomly from
chip to chip. As such they are wholly inappropriate for use in general
purpose software like glibc. There is a reason that these registers are
buried behind APIs like perfctr, perfmon, oprofile.
As I said the implementation for powerpc32/64 will be based on the
architected timebase register.
Steven J. Munroe
Linux on Power Toolchain Architect
IBM Corporation, Linux Technology Center