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Re: [PATCH] hp-timing for ppc32/64

Benjamin Herrenschmidt <> wrote on 10/17/2005 
04:41:09 PM:

> On Mon, 2005-10-17 at 10:47 -0500, Steve Munroe wrote:
> > wrote on 10/15/2005 11:21:09 AM:
> > 
> > > Steve,
> > > 
> > > Is there any advantage to having access to a higher frequency 
> > > than the time base if it exists in the CPU for this functionality?
> > >
> > 
> > I am using the timebase register per the PowerPC Architecture.
> > 
> > What timer would have a higher frequency then CPU_clock/8 ? Which is 
> > timebase for all the POWER3/POWER4/POWER5/970 implementations. 
> > as the accessing the timebase requires at least 10 cycles!
> Note that some CPUs like the 970 can have an externally clocked
> timebase. Apple uses this feature to make the CPU immune to bus/cpu
> frequency slewing, they use a 33Mhz clock for that. 
The 970 does not implement a alternate timebase. So for 970 the timebase 
is the highest frequency counter available. 
It seems that Apple choose 33MHz to meet the minimum (slowest)CPU-clock / 
32 timebase. But that was their choice. The IBM hardware seems to be 
holding to the CPU_clock / 8 timebase (including 970 based JS20).

Steven J. Munroe
Linux on Power Toolchain Architect
IBM Corporation, Linux Technology Center

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