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Re: [PATCH] Native POSIX Thread Library(NPTL) ARM Supporting Patches (1/3)
> Wouldn't it be useful to always map the second page of a process (page
> 1) to a per-task/thread specific ro page where that information can be
> contained, as well as other stuff we usually get from the kernel,
> being kind of overkill (like for example, PID, date? and some other
> statistics/data from the process).
mips-Irix used to have something like this, so this is not without
precedent. The drawback is that the TLB is then no longer the same
for different threads in a process, so I presume the context switch
time between those threads would go up. By how much I do not know,
but this is the time has to be weighed against (a) the system call
overhead and (b) Philip Blundell's suggestion of performing "only" a
pointer write on each context switch.