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Re: [PATCH] ppc32 dl-machine.c
> > ***except that memory accesses caused by those instructions need not have been performed
> > with respect to other processors and mechanisms.***
> >
> ...
>
> Yes, but we don't care about other processors. So long as the local
> icache line is cleared at the point of the isync, and so long as the
> icache line on other processors gets cleared sometime, everything will
> work. It's not like this code is (for instance) loading an object for
> a thread running on another processor that could try to run the code
> before a sync is executed.
It also says (elsewhere) that external cache is one example of such a
"mechanism", and surprise surprise, on the G4 the L2 needs the sync.
You only need one sync btw, but it has to be _after_ the icbi, not before.
There's no need for a sync inbetween the dcbst and the icbi.
> This code can't flush the icache on other processors if icbi isn't
> broadcast; it doesn't have access to them.
As I said, dcbf will probably flush it on other cpu's; but in principal,
there is _no_ mechanism that will flush other cpu's (or external cache etc).
Cheers,
Segher