This is the mail archive of the libc-alpha@sources.redhat.com mailing list for the glibc project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [libc-alpha] Re: PATCH: Fix ll/sc for mips


> From: Andreas Schwab <schwab@suse.de>
> Date: Fri, 01 Feb 2002 11:49:22 +0100

> There is no way to find out anything about intermediate values of *p when
> compare_and_swap returns zero.  The value of *p can change anytime, even
> if it only was different from oldval just at the time compare_and_swap did
> the comparison.  So there is zero chance that a spurious failure of
> compare_and_swap breaks anything.

Something to watch out for, though, is livelock.  Consider the
situation in which two processors are competing for a cache line, and
both only win at the 'wrong' time: when computing a new value to be
passed to compare_and_swap rather than when actually trying to perform
the compare_and_swap.  This is why on powerpc the loop is coded in the
asm statement.

-- 
- Geoffrey Keating <geoffk@geoffk.org> <geoffk@redhat.com>


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]