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[PATCH] arm reversible : progress <patch_1_phase_1>
- From: paawan oza <paawan1982 at yahoo dot com>
- To: "gdb at sourceware dot org" <gdb at sourceware dot org>
- Date: Wed, 2 Feb 2011 01:28:44 -0800 (PST)
- Subject: [PATCH] arm reversible : progress <patch_1_phase_1>
Hi all,
As I thought, I would be working on arm insn part first and then linux ABI part
first.
working with arm and thumb insn, I have come up with patch_1 of my phase 1
activity.
which mainly includes design, few insns, and framework on which I will relying
on rest of the implementation.
few arm insns are implemented and in place, and I am able to debug following
samle program too.
PS: I am posting this patch, not with the intension of comletion or getting it
in mainline. but I thought If I post early I may get some valuable suggestions
and inputs regarding design and data structures, or have missed to consider some
arch related issues. I will get to know early before I go forward.
please also ignore coding guidelines as it will be corrected in due timeline.
any inputs and suggestions are welcome.
the samle program is as below.
#include <stdio.h>
void main()
{
int s;
s = 10;
s = 15;
s = 20;
s = -30;
s = 88;
}
<PATCH>
diff -urN arm_orig/arm-linux-tdep.c arm_new/arm-linux-tdep.c
--- arm_orig/arm-linux-tdep.c 2011-02-02 14:22:52.000000000 +0530
+++ arm_new/arm-linux-tdep.c 2011-02-02 14:23:03.000000000 +0530
@@ -998,6 +998,9 @@
set_gdbarch_fetch_tls_load_module_address (gdbarch,
svr4_fetch_objfile_link_map);
+ /* Enable process record */
+ set_gdbarch_process_record(gdbarch, arm_process_record);
+
tramp_frame_prepend_unwinder (gdbarch,
&arm_linux_sigreturn_tramp_frame);
tramp_frame_prepend_unwinder (gdbarch,
diff -urN arm_orig/arm-tdep.c arm_new/arm-tdep.c
--- arm_orig/arm-tdep.c 2011-02-02 14:22:53.000000000 +0530
+++ arm_new/arm-tdep.c 2011-02-02 14:23:03.000000000 +0530
@@ -54,8 +54,11 @@
#include "gdb_assert.h"
#include "vec.h"
+#include "record.h"
+
#include "features/arm-with-m.c"
+
static int arm_debug;
/* Macros for setting and testing a bit in a minimal symbol that marks
@@ -7929,3 +7932,576 @@
NULL, /* FIXME: i18n: "ARM debugging is %s. */
&setdebuglist, &showdebuglist);
}
+
+
+
+/* arm-reversible process reacord data structures */
+
+#define NO_OF_TYPE_OF_ARM_INSNS 8
+#define ARM_RECORD_ARCH_LIST_ADD_REG(regnum) \
+ record_arch_list_add_reg (arm_record.regcache, regnum)
+
+#define GET_REG_VAL(REGCACHE,NO,BUF) regcache_raw_read (REGCACHE, NO, BUF);
+
+#define IS_IT_ARM_INSN(X) ((X & 0x00000010) >> 4)
+#define ARM_PARSE_INSN(X,BIT_POS,NO_OF_BITS) \
+ ((X >> (BIT_POS-1)) & (0xFFFFFFFF >> ((sizeof(uint32_t)*8) - \
+ NO_OF_BITS)))
+
+/* arm_handle_data_proc_imm_insn */
+#define INSN_S_BIT_NUM 21
+#define ARM_BIT_SET(X, NUM) (((X >> (NUM-1)) & 0x00000001) == 1)
+
+
+int arm_handle_data_proc_misc_load_str_insn (void*);
+int arm_handle_data_proc_misc_load_str_insn(void*);
+int arm_handle_data_proc_imm_insn(void*);
+int arm_handle_ld_st_imm_offset_insn(void*);
+int arm_handle_ld_st_reg_offset_insn(void*);
+int arm_hamdle_ld_st_multiple_insn(void*);
+int arm_handle_brn_insn(void*);
+int arm_handle_coproc_insn(void*);
+int arm_handle_coproc_data_proc_insn(void*);
+
+int (*const arm_handle_insn[NO_OF_TYPE_OF_ARM_INSNS]) (void*) =
+{
+ arm_handle_data_proc_misc_load_str_insn,
+ arm_handle_data_proc_imm_insn,
+ arm_handle_ld_st_imm_offset_insn,
+ arm_handle_ld_st_reg_offset_insn,
+ arm_hamdle_ld_st_multiple_insn,
+ arm_handle_brn_insn,
+ arm_handle_coproc_insn,
+ arm_handle_coproc_data_proc_insn
+};
+
+struct arm_mem_r
+{
+ uint32_t len;
+ CORE_ADDR addr;
+};
+
+typedef struct arm_insn_decode_record_t
+{
+ struct gdbarch *gdbarch;
+ struct regcache *regcache;
+ CORE_ADDR this_addr; /* address of the insn being decoded */
+ uint32_t arm_insn; /* should accomodate thumb */
+ uint32_t cond; /* condition code */
+ uint32_t id; /* type of insn */
+ uint32_t opcode; /* insn opcode */
+ uint32_t decode; /* insn decode bits */
+ uint32_t *arm_regs; /* registers to be saved for this record */
+ struct arm_mem_r *arm_mems; /* memory to be saved for this record
*/
+} arm_insn_decode_record;
+
+
+int decode_insn(arm_insn_decode_record *arm_record, uint32_t insn_size)
+{
+ union
+ {
+ uint32_t s_word;
+ gdb_byte buf[insn_size];
+ } u_buf;
+
+ if (target_read_memory (arm_record->this_addr, &u_buf.buf[0],
insn_size))
+ {
+ if (record_debug)
+ printf_unfiltered (_("Process record: error reading memory at "
+ "addr %s len = %d.\n"),
+ paddress (arm_record->gdbarch, arm_record->this_addr), insn_size);
+ return -1;
+ }
+ else
+ {
+ arm_record->arm_insn = u_buf.s_word;
+ arm_record->cond = ARM_PARSE_INSN (arm_record->arm_insn,29,4);
+ arm_record->id = ARM_PARSE_INSN (arm_record->arm_insn,26,3);
+
+ if (0b1111 == arm_record->cond)
+ {
+ /* Version5 and above support this, so handle this as well.
*/
+ }
+ else
+ {
+ arm_handle_insn[arm_record->id]((void*)arm_record);
+ }
+ }
+ return 0;
+}
+
+/* Parse the current instruction and record the values of the registers and
+ memory that will be changed in current instruction to "record_arch_list".
+ Return -1 if something is wrong. */
+
+int arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
+ CORE_ADDR insn_addr)
+{
+
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ int no_of_rec=0;
+
+ union
+ {
+ uint32_t s_word;
+ gdb_byte buf[4];
+ } u_buf;
+
+ arm_insn_decode_record arm_record;
+
+ memset (&arm_record, 0, sizeof (arm_insn_decode_record));
+ arm_record.regcache = regcache;
+ arm_record.this_addr = insn_addr;
+ arm_record.gdbarch = gdbarch;
+
+
+ if (record_debug > 1)
+ fprintf_unfiltered (gdb_stdlog, "Process record: arm_process_record "
+ "addr = %s\n",
+ paddress (gdbarch, arm_record.this_addr));
+
+ /* check the insn, whether it is thumb or arm one */
+ GET_REG_VAL (arm_record.regcache, ARM_PS_REGNUM, &u_buf.buf[0]);
+ if (IS_IT_ARM_INSN (u_buf.s_word))
+ {
+ /* we are decoding arm insn */
+ decode_insn (&arm_record, 4);
+ }
+ else
+ {
+ /* we are decoding thumb insn */
+ decode_insn (&arm_record, 2);
+ }
+
+ /* record registers */
+ ARM_RECORD_ARCH_LIST_ADD_REG(ARM_PC_REGNUM);
+ if(arm_record.arm_regs)
+ {
+ for(no_of_rec=1;no_of_rec<=arm_record.arm_regs[0];no_of_rec++)
+ {
+ if(ARM_RECORD_ARCH_LIST_ADD_REG(arm_record.arm_regs[no_of_rec]))
+ {
+ return -1;
+ }
+ }
+ }
+ /* record memories */
+ if(arm_record.arm_mems)
+ {
+ for(no_of_rec=1;no_of_rec<=arm_record.arm_mems[0].len;no_of_rec++)
+ {
+ if(record_arch_list_add_mem((CORE_ADDR)arm_record.arm_mems[no_of_rec].\
+ addr,arm_record.arm_mems[no_of_rec].len))
+ {
+ return -1;
+ }
+ }
+ }
+
+ if (record_arch_list_add_end ())
+ {
+ return -1;
+ }
+ return 0;
+}
+
+int arm_handle_data_proc_misc_load_str_insn(void *data)
+{
+
+ arm_insn_decode_record *arm_insn_r = (arm_insn_decode_record*) data;
+ struct gdbarch_tdep *tdep = gdbarch_tdep ((struct gdbarch*)
arm_insn_r->gdbarch);
+ struct regcache *reg_cache = (struct regcache*) arm_insn_r->regcache;
+
+ union
+ {
+ uint32_t s_word;
+ gdb_byte buf[4];
+ }u_buf[2];
+
+ uint32_t reg_val1=0,reg_val2=0;
+ uint32_t reg_src1=0,reg_src2=0,reg_dest=0;
+ uint32_t immed_high=0,immed_low=0,offset_8=0,tgt_mem_addr=0;
+
+ arm_insn_r->opcode = ARM_PARSE_INSN(arm_insn_r->arm_insn,22,4);
+ arm_insn_r->decode = ARM_PARSE_INSN(arm_insn_r->arm_insn,5,4);
+
+ if (ARM_BIT_SET(arm_insn_r->arm_insn, INSN_S_BIT_NUM))
+ {
+ /* data processing insn /multiply sinsn */
+ if(9 == arm_insn_r->decode)
+ {
+ /* handle multiply instructions */
+ /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL */
+ if((0 == arm_insn_r->opcode) || (1 == arm_insn_r->opcode))
+ {
+ /* handle MLA and MUL */
+ arm_insn_r->arm_regs = (uint32_t*)xmalloc(sizeof(uint32_t)*3);
+ arm_insn_r->arm_regs[0] = 2;
+ arm_insn_r->arm_regs[1] =
ARM_PARSE_INSN(arm_insn_r->arm_insn,17,4);
+ arm_insn_r->arm_regs[2] = ARM_PS_REGNUM;
+ }
+ else if((4 <= arm_insn_r->opcode) && (7 >= arm_insn_r->opcode))
+ {
+ /* handle SMLAL, SMULL, UMLAL, UMULL */
+ arm_insn_r->arm_regs = (uint32_t*)xmalloc(sizeof(uint32_t)*4);
+ arm_insn_r->arm_regs[0] = 3;
+ arm_insn_r->arm_regs[1] =
ARM_PARSE_INSN(arm_insn_r->arm_insn,17,4);
+ arm_insn_r->arm_regs[2] =
ARM_PARSE_INSN(arm_insn_r->arm_insn,13,4);
+ arm_insn_r->arm_regs[3] = ARM_PS_REGNUM;
+
+ }
+ }
+ else if((11 == arm_insn_r->decode) || (13 == arm_insn_r->decode))
+ {
+ /* handle misc load insns, as 20th bit (L = 1) */
+ /* LDR insn has a capability to do branching, if
+ MOV LR, PC is precedded by LDR insn having Rn as R15
+ in that case, it emulates branch and link insn, and hence we
+ need to save CSPR and PC as well. */
+ reg_dest = ARM_PARSE_INSN(arm_insn_r->arm_insn,13,4);
+ if(15 != reg_dest)
+ {
+ arm_insn_r->arm_regs = (uint32_t*)xmalloc(sizeof(uint32_t)*2);
+ arm_insn_r->arm_regs[0] = 1;
+ arm_insn_r->arm_regs[1] =
ARM_PARSE_INSN(arm_insn_r->arm_insn,13,4);
+ }
+ else
+ {
+ arm_insn_r->arm_regs = (uint32_t*)xmalloc(sizeof(uint32_t)*3);
+ arm_insn_r->arm_regs[0] = 2;
+ arm_insn_r->arm_regs[1] =
ARM_PARSE_INSN(arm_insn_r->arm_insn,13,4);
+ arm_insn_r->arm_regs[2] = ARM_PS_REGNUM;
+ }
+ }
+ else
+ {
+ /* normal data processing insns */
+ /* out of 11 shifter operands mode, all the insn modifies destination
+ register, which is specified by 13-16 decode */
+ arm_insn_r->arm_regs = (uint32_t*)xmalloc(sizeof(uint32_t)*3);
+ arm_insn_r->arm_regs[0] = 2;
+ arm_insn_r->arm_regs[0] = ARM_PARSE_INSN(arm_insn_r->arm_insn,13,4);
+ arm_insn_r->arm_regs[1] = ARM_PS_REGNUM;
+ }
+ }
+ else
+ {
+ /* handle misc, swap insns, and store instructions as 20th bit ((L = 0)
*/
+ if(9 == arm_insn_r->decode)
+ {
+ /* Handling SWP, SWPB */
+ /* these insns, changes register and memory as well */
+ if((8 == arm_insn_r->opcode) || (10 == arm_insn_r->opcode))
+ {
+ /* SWP or SWPB insn */
+ arm_insn_r->arm_regs = (uint32_t*)xmalloc(sizeof(uint32_t)*2);
+ arm_insn_r->arm_mems = (struct arm_mem_r *)xmalloc(sizeof(struct
+ arm_mem_r)*2);
+ /* get memory address given by Rn */
+ reg_src1 = ARM_PARSE_INSN(arm_insn_r->arm_insn,17,4);
+ GET_REG_VAL(reg_cache,reg_src1,&u_buf[0].buf[0]);
+ arm_insn_r->arm_mems[0].len = 1;
+ /* SWP insn ?, swaps word */
+ if (8 == arm_insn_r->opcode)
+ {
+ arm_insn_r->arm_mems[1].len = 4;
+ }
+ else
+ {
+ /* SWPB insn, swaps only byte */
+ arm_insn_r->arm_mems[1].len = 1;
+ }
+ arm_insn_r->arm_mems[1].addr = u_buf[0].s_word;
+ arm_insn_r->arm_regs[0] = 1;
+ arm_insn_r->arm_regs[1] =
ARM_PARSE_INSN(arm_insn_r->arm_insn,13,4);
+ }
+ }
+ else if(3 == arm_insn_r->decode)
+ {
+ /* handle BLX, branch and link/exchange */
+ if(9 == arm_insn_r->opcode)
+ {
+ /* branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
+ and R14 stores the return address */
+ arm_insn_r->arm_regs = (uint32_t*)xmalloc(sizeof(uint32_t)*3);
+ arm_insn_r->arm_regs[0] = 2;
+ arm_insn_r->arm_regs[1] = ARM_PS_REGNUM;
+ arm_insn_r->arm_regs[2] = ARM_LR_REGNUM;
+ }
+ }
+ else if(7 == arm_insn_r->decode)
+ {
+ /* handle enhanced software breakpoint insn, BKPT */
+ /* CPSR is changed to be executed in ARM state, disabling normal
+ interrupts, entering abort mode */
+ /* accorindly to high vector configuration PC is set accordingly */
+ /* Oza: FIX ME ? what if user hit breakpoint and type reverse, in
+ that case, we need to go back with previous CSPR and
+ Program Counter. */
+ arm_insn_r->arm_regs = (uint32_t*)xmalloc(sizeof(uint32_t)*2);
+ arm_insn_r->arm_regs[0] = 1;
+ arm_insn_r->arm_regs[0] = ARM_PS_REGNUM;
+ }
+ else if(13 == arm_insn_r->decode)
+ {
+ /* handle enhanced store insns and LDRD DSP insn and */
+ /* let us begin according to addressing modes for store insns */
+
+ if((14 == arm_insn_r->opcode) || (10 == arm_insn_r->opcode))
+ {
+ /* 1) handle misc store, immediate offset */
+ immed_low = ARM_PARSE_INSN(arm_insn_r->arm_insn,1,4);
+ immed_high = ARM_PARSE_INSN(arm_insn_r->arm_insn,9,4);
+ reg_src1 = ARM_PARSE_INSN(arm_insn_r->arm_insn,17,4);
+ GET_REG_VAL(reg_cache,reg_src1,&u_buf[0].buf[0]);
+ if(15 == reg_src1)
+ {
+ /* if R15 was used as Rn, hence current PC+8 */
+ u_buf[0].s_word = u_buf[0].s_word + 8;
+ }
+ offset_8 = (immed_high << 4) | immed_low;
+ /* calculate target store address */
+ if(14 == arm_insn_r->opcode)
+ {
+ tgt_mem_addr = u_buf[0].s_word + offset_8;
+ }
+ else
+ {
+ tgt_mem_addr = u_buf[0].s_word - offset_8;
+ }
+ arm_insn_r->arm_mems = (struct arm_mem_r *)xmalloc(sizeof(struct
+ arm_mem_r)*2);
+ arm_insn_r->arm_mems[0].len = 1;
+ arm_insn_r->arm_mems[1].len = 2;
+ arm_insn_r->arm_mems[1].addr = tgt_mem_addr;
+ }
+ else if((12 == arm_insn_r->opcode) || (8 == arm_insn_r->opcode))
+ {
+ /* 2) store, register offset */
+ /* get Rm */
+ reg_src1 = ARM_PARSE_INSN(arm_insn_r->arm_insn,1,4);
+ /* get Rn */
+ reg_src2 = ARM_PARSE_INSN(arm_insn_r->arm_insn,17,4);
+ GET_REG_VAL(reg_cache,reg_src1,&u_buf[0].buf[0]);
+
GET_REG_VAL(reg_cache,reg_src2,&u_buf[1].buf[0]);
+ if(15 == reg_src2)
+ {
+ /* if R15 was used as Rn, hence current PC+8 */
+ u_buf[0].s_word = u_buf[0].s_word + 8;
+ }
+ /* calculate target store address, Rn +/- Rm, register offset */
+ if(12 == arm_insn_r->opcode)
+ {
+ tgt_mem_addr = u_buf[0].s_word + u_buf[1].s_word;
+ }
+ else
+ {
+ tgt_mem_addr = u_buf[1].s_word - u_buf[0].s_word;
+ }
+ arm_insn_r->arm_mems = (struct arm_mem_r *)xmalloc(sizeof(struct
+ arm_mem_r)*2);
+ arm_insn_r->arm_mems[0].len = 1;
+ arm_insn_r->arm_mems[1].len = 2;
+ arm_insn_r->arm_mems[1].addr = tgt_mem_addr;
+ }
+ else if((11 == arm_insn_r->opcode) || (15 == arm_insn_r->opcode)
+ || (2 == arm_insn_r->opcode) || (6 == arm_insn_r->opcode))
+ {
+ /* 3) store, immediate pre-indexed */
+ /* 5) store, immediate post-indexed */
+ immed_low = ARM_PARSE_INSN(arm_insn_r->arm_insn,1,4);
+ immed_high = ARM_PARSE_INSN(arm_insn_r->arm_insn,9,4);
+ offset_8 = (immed_high << 4) | immed_low;
+ reg_src1 = ARM_PARSE_INSN(arm_insn_r->arm_insn,17,4);
+ GET_REG_VAL(reg_cache,reg_src1,&u_buf[0].buf[0]);
+ /* calculate target store address, Rn +/- Rm, register offset */
+ if((15 == arm_insn_r->opcode) || (6 == arm_insn_r->opcode))
+ {
+ tgt_mem_addr = u_buf[0].s_word + offset_8;
+ }
+ else
+ {
+ tgt_mem_addr = u_buf[0].s_word - offset_8;
+ }
+ arm_insn_r->arm_mems = (struct arm_mem_r *)xmalloc(sizeof(struct
+ arm_mem_r)*2);
+ arm_insn_r->arm_mems[0].len = 1;
+ arm_insn_r->arm_mems[1].len = 2;
+ arm_insn_r->arm_mems[1].addr = tgt_mem_addr;
+ /* record Rn also as it changes */
+ arm_insn_r->arm_regs = (uint32_t*)xmalloc(sizeof(uint32_t)*2);
+ arm_insn_r->arm_regs[0] = 1;
+ arm_insn_r->arm_regs[1] =
ARM_PARSE_INSN(arm_insn_r->arm_insn,17,4);
+
+ }
+ else if((9 == arm_insn_r->opcode) || (13 == arm_insn_r->opcode)
+ || (0 == arm_insn_r->opcode) || (4 == arm_insn_r->opcode))
+ {
+ /* 4) store, register pre-indexed */
+ /* 6) store, register post -indexed */
+ reg_src1 = ARM_PARSE_INSN(arm_insn_r->arm_insn,1,4);
+ reg_src2 = ARM_PARSE_INSN(arm_insn_r->arm_insn,17,4);
+ GET_REG_VAL(reg_cache,reg_src1,&u_buf[0].buf[0]);
+ GET_REG_VAL(reg_cache,reg_src2,&u_buf[1].buf[0]);
+ /* calculate target store address, Rn +/- Rm, register offset */
+ if((13 == arm_insn_r->opcode) || (4 == arm_insn_r->opcode))
+ {
+ tgt_mem_addr = u_buf[0].s_word + u_buf[1].s_word;
+ }
+ else
+ {
+ tgt_mem_addr = u_buf[1].s_word - u_buf[0].s_word;
+ }
+ arm_insn_r->arm_mems = (struct arm_mem_r *)xmalloc(sizeof(struct
+ arm_mem_r)*2);
+ arm_insn_r->arm_mems[0].len = 1;
+ arm_insn_r->arm_mems[1].len = 2;
+ arm_insn_r->arm_mems[1].addr = tgt_mem_addr;
+ /* record Rn also as it changes */
+ arm_insn_r->arm_regs = (uint32_t*)xmalloc(sizeof(uint32_t)*2);
+ arm_insn_r->arm_regs[0] = 1;
+ arm_insn_r->arm_regs[1] =
ARM_PARSE_INSN(arm_insn_r->arm_insn,17,4);
+ }
+ /* DSP LDRD TBD */
+ }
+ else if(1 == arm_insn_r->decode)
+ {
+ /* handle BLX, branch and link/exchange */
+ if(2 == arm_insn_r->opcode)
+ {
+ /* branch is chosen by setting T bit of CSPR, bitp[0] of Rm */
+ arm_insn_r->arm_regs = (uint32_t*)xmalloc(sizeof(uint32_t)*2);
+ arm_insn_r->arm_regs[0] = 1;
+ arm_insn_r->arm_regs[1] = ARM_PS_REGNUM;
+ }
+ else if(11 == arm_insn_r->opcode)
+ {
+ /* count leading zeros: CLZ */
+ arm_insn_r->arm_regs = (uint32_t*)xmalloc(sizeof(uint32_t)*2);
+ arm_insn_r->arm_regs[0] = 1;
+ arm_insn_r->arm_regs[1] =
ARM_PARSE_INSN(arm_insn_r->arm_insn,13,4);
+ }
+ }
+ else if((0 == arm_insn_r->opcode) || (4 == arm_insn_r->opcode))
+ {
+ /* handle MRS insn*/
+ arm_insn_r->arm_regs = (uint32_t*)xmalloc(sizeof(uint32_t)*2);
+ arm_insn_r->arm_regs[0] = 1;
+ arm_insn_r->arm_regs[1] = ARM_PARSE_INSN(arm_insn_r->arm_insn,13,4);
+ }
+ else if ((9 == arm_insn_r->opcode) || (11 == arm_insn_r->opcode))
+ {
+ /* handle MSR insn*/
+ arm_insn_r->arm_regs = (uint32_t*)xmalloc(sizeof(uint32_t)*2);
+ if (9 == arm_insn_r->opcode)
+ {
+ /*CSPR is going to be changed */
+ arm_insn_r->arm_regs[0] = 1;
+ arm_insn_r->arm_regs[1] = ARM_PS_REGNUM;
+ }
+ else
+ {
+ /* SPSR is going to be changed */
+ /* OZA FIX ME ? how to read SPSR value ?*/
+ }
+ }
+ }
+ return 0;
+}
+
+int arm_handle_data_proc_imm_insn(void *data)
+{
+ arm_insn_decode_record *arm_insn_r = (arm_insn_decode_record*) data;
+ struct gdbarch_tdep *tdep = \
+ gdbarch_tdep ((struct gdbarch*) arm_insn_r->gdbarch);
+ struct regcache *reg_cache = (struct regcache*) arm_insn_r->regcache;
+
+ uint32_t reg_val1=0,reg_val2=0;
+ uint32_t reg_src1=0,reg_src2=0,reg_dest=0;
+ uint32_t immed_high=0,immed_low=0,offset_8=0,tgt_mem_addr=0;
+
+ arm_insn_r->opcode = ARM_PARSE_INSN(arm_insn_r->arm_insn,22,4);
+ arm_insn_r->decode = ARM_PARSE_INSN(arm_insn_r->arm_insn,5,4);
+
+ if (ARM_BIT_SET(arm_insn_r->arm_insn, INSN_S_BIT_NUM))
+ {
+ /* data processing insn, e.g. MOV */
+ arm_insn_r->arm_regs = (uint32_t*)xmalloc(sizeof(uint32_t)*3);
+ arm_insn_r->arm_regs[0] = 2;
+ arm_insn_r->arm_regs[1] = ARM_PARSE_INSN(arm_insn_r->arm_insn,13,4);
+ arm_insn_r->arm_regs[2] = ARM_PS_REGNUM;
+ }
+ return 0;
+}
+
+int arm_handle_ld_st_imm_offset_insn(void *data)
+{
+ arm_insn_decode_record *arm_insn_r = (arm_insn_decode_record*) data;
+ struct gdbarch_tdep *tdep = \
+ gdbarch_tdep ((struct gdbarch*) arm_insn_r->gdbarch);
+ struct regcache *reg_cache = (struct regcache*) arm_insn_r->regcache;
+
+ uint32_t reg_val1=0,reg_val2=0;
+ uint32_t reg_src1=0,reg_src2=0,reg_dest=0;
+ uint32_t immed_high=0,immed_low=0,offset_12=0,tgt_mem_addr=0;
+
+ union
+ {
+ uint32_t s_word;
+ gdb_byte buf[4];
+ }u_buf;
+
+ arm_insn_r->opcode = ARM_PARSE_INSN(arm_insn_r->arm_insn,22,4);
+ arm_insn_r->decode = ARM_PARSE_INSN(arm_insn_r->arm_insn,5,4);
+
+ /* Oza: as of now only STR is getting implemented for demo */
+ reg_src1= ARM_PARSE_INSN(arm_insn_r->arm_insn,17,4);
+ offset_12 = ARM_PARSE_INSN(arm_insn_r->arm_insn,1,12);
+ GET_REG_VAL(reg_cache,reg_src1,&u_buf.buf[0]);
+ if (ARM_BIT_SET(arm_insn_r->arm_insn,24))
+ {
+ tgt_mem_addr = u_buf.s_word + offset_12;
+ }
+ else
+ {
+ tgt_mem_addr = u_buf.s_word - offset_12;
+ }
+
+ arm_insn_r->arm_mems = (struct arm_mem_r *)xmalloc(sizeof(struct
+ arm_mem_r)*2);
+ arm_insn_r->arm_mems[0].len = 1;
+ arm_insn_r->arm_mems[1].len = 4;
+ arm_insn_r->arm_mems[1].addr = tgt_mem_addr;
+ return 0;
+}
+
+int arm_handle_ld_st_reg_offset_insn(void *data)
+{
+ /* TBD */
+ return 0;
+}
+
+int arm_hamdle_ld_st_multiple_insn(void *data)
+{
+ /* TBD */
+ return 0;
+}
+
+int arm_handle_brn_insn(void *data)
+{
+ /* TBD */
+ return 0;
+}
+
+int arm_handle_coproc_insn(void *data)
+{
+ /* TBD */
+ return 0;
+}
+
+int arm_handle_coproc_data_proc_insn(void *data)
+{
+ /* TBD */
+ return 0;
+}
Regards,
Oza.
----- Original Message ----
From: paawan oza <paawan1982@yahoo.com>
To: Michael Snyder <msnyder@vmware.com>
Cc: "gdb@sourceware.org" <gdb@sourceware.org>
Sent: Tue, February 1, 2011 8:50:51 AM
Subject: Re: arm reversible execution query
Hi Michael,
thank you for your reply.
I think you are referring to below line. in process_record.
I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM);
if (record_arch_list_add_end ())
return -1;
I got it that it has to be saved explicitly by process record arch level.
Thanks,
Oza.
----- Original Message ----
From: Michael Snyder <msnyder@vmware.com>
To: paawan oza <paawan1982@yahoo.com>
Cc: "gdb@sourceware.org" <gdb@sourceware.org>
Sent: Tue, February 1, 2011 12:23:14 AM
Subject: Re: arm reversible execution query
paawan oza wrote:
>
> Hi all,
>
> I have been wroking on arm-reversible implementation and doing arm insn part. I
>
>am done with framework, and supporting 30-40% on insns till now.
> when I simply test on arm board, I find that,
>
> all the memory and registers are replayed correctly and recording is
happening.
> but,
> do I need to save Program counter explicitly ?
> doesnt gdb reversible framework take care of changing pc when I apply
>reverse-stepi/nexti command ?
>
> as i386-tdep.c, does not seem to be saving PC explicitly.
>
> please clarify.
i386-tdep.c does save the PC ($eip), at the end of function i386_process_record.
If you don't save the PC, how can you do a reverse jump?