how to model insns that trigger exceptions/interrupts

[Mike Frysinger <vapier at gentoo dot org>]

ive looked over the current interrupt support (hw_port_event and such), as 
well as the current sim event code, but i cant seem to figure out how to model 
instructions that trigger exceptions/interrupts while in the operating 
environment.

the interrupt framework requires an interrupt source (output_port) in order to 
connect to a device that accepts interrupts (input_port).  but how can the 
source of the interrupt be the simulated instruction when there is no hardware 
backing up SIM_CPU ?  for example, the Blackfin ISA includes a "RAISE #" 
instruction which allows the instruction set to trigger the specified 
interrupt number directly.  when the Blackfin sim decodes the "RAISE #", it 
cant call hw_port_event() on the interrupt # because the insn decoding step 
isnt running in the content of any hardware device (afaik), and 
hw_port_event() wont accept a NULL hw device.  so what should be done here to 
deliver the interrupt to the interrupt controller ?  using glue and/or pal is 
not desirable as it seems to require mapping the devices into the address map 
which "pollutes" the simulation wrt working the same as the real hardware.

in a similar vein, how can one simulate exceptions ?  interrupts are easy as 
those may be triggered asynchronous to the program flow (so after any 
instruction is fetched/decoded/committed).  exceptions though fire after the 
decode step but before the commit so that no CPU state is ever changed.  in 
the bigger picture of things, an exception is still a normal simulator event, 
so should the processor-specific sim part basically schedule an "exception 
event" and then return immediately before touching any cpu state ?  or is 
there some common sim function i can leverage that i simply missed ?
-mike

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