Re: [Fwd: a small bug in the arm simulator]

[Nick Clifton <nickc at redhat dot com>]

Hi Jens-Christian,
 
> Some time ago I have complained, that the arm simulator does not
> know software traps.

Well it does - but not perfectly.

The reason is that the arm simulator is *not* a full arm architecture
simulator.  It is just an instruction level simulator.  It is enough
to allow the simulation of ordinary programs (that do not do complex
I/O or make use of OS services) and the test programs for gcc, g++
etc.

If you need a fully fledged, cycle accurate, architecture accurate
simulator you should consider contacting ARM for their commercial
product, or ... fixing the GNU simulator so that it is architecture
accurate.

> - 0x201aa8c <interrupt_end_os_schedule_0+12>:	 orr    r0, r0, #146
> - 0x201aa90 <interrupt_end_os_schedule_0+16>:	 msr	CPSR_fc, r0
> 
> The bug is located in 0x201aa90. It is not writing anything at all to
> the cpsr.

Are you using the latest sources from the CVS repository ?  Quite a
few bug fixes have been applied to the simulator over the last few
months, so it is possible that this might have been fixed.

If it has not been fixed, then I would suggest you try debugging the
simulator.  It is relatively straightforward.  In this case I would
suggest that you look at the code in the file sim/arm/armsupp.c which
contains most of the routines for handling state changes.

Cheers
        Nick