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Re: [PATCH] riscv: add gdbserver support
- From: Guo Ren <guoren at kernel dot org>
- To: Jim Wilson <jimw at sifive dot com>
- Cc: jiangshuai_li at c-sky dot com, Maciej Rozycki <macro at wdc dot com>, Andrew Burgess <andrew dot burgess at embecosm dot com>, gdb-patches at sourceware dot org, 夏立方 <lifang_xia at c-sky dot com>, yunhai_shang <yunhai_shang at c-sky dot com>
- Date: Wed, 22 Jan 2020 10:15:37 +0800
- Subject: Re: [PATCH] riscv: add gdbserver support
- References: <00e401d5cb52$63a4d000$2aee7000$@c-sky.com> <CAFyWVaa7ADP_SmBVoan9AOkWK9parEz5EENZZL5vY+_GcD9SrA@mail.gmail.com>
Hi Jim,
On Tue, Jan 21, 2020 at 7:04 AM Jim Wilson <jimw@sifive.com> wrote:
>
> > 3. vector regitsers r/w
>
> The vector registers are still in draft form, and are subject to
> change. I'd rather not add support for draft features upstream, as
> then we are stuck supporting draft versions of the ISA forever. Also,
> we still don't have a proposal for DWARF register numbers for the
> vector registers.
In fact, both T-HEAD XuanTie C910 and Andes 27-series CPU cores claim
to support vector extensions, which is good for riscv-v extenstion.
Many complex linux vector development/test-suite need linux/gdb/glibc
to support the vector-regs' context.
So I think these basic functions for linux/gdb/glibc should be merged
in advance, rather than waiting for the entire vector spec to freeze.
After all, register save / restore is only a small part of riscv-v and
very basic, maybe the part of registers(abi) could be frozen in the
vector spec in advance.
Here is the linux riscv-v port V2 for task_switch, singal, ptrace: [1]
[1]: https://lore.kernel.org/linux-riscv/20200116143029.31441-4-guoren@kernel.org/
Best Regrads
Guo Ren