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Re: [PATCH] gdb/riscv: Add target description support
- From: Joel Brobecker <brobecker at adacore dot com>
- To: Andrew Burgess <andrew dot burgess at embecosm dot com>
- Cc: Tom Tromey <tom at tromey dot com>, gdb-patches at sourceware dot org, jimw at sifive dot com, palmer at sifive dot com, jhb at FreeBSD dot org
- Date: Tue, 26 Feb 2019 15:55:10 +0400
- Subject: Re: [PATCH] gdb/riscv: Add target description support
- References: <20181108160745.24600-1-andrew.burgess@embecosm.com> <20181114145756.GM16539@embecosm.com> <87r2bz67ol.fsf@tromey.com> <20190223203958.GA15942@embecosm.com>
Hi Andrew,
> [PATCH] gdb/riscv: Use legacy register numbers in default target description
>
> When the target description support was added to RISC-V, the register
> numbers assigned to the fflags, frm, and fcsr control registers in the
> default target descriptions didn't match the register numbers used by
> GDB before the target description support was added.
>
> What this means is that if a tools exists in the wild that is using
> hard-coded register number, setup to match GDB's old behaviour, then
> this will have been broken (for fflags, frm, and fcsr) by the move to
> target descriptions. QEMU is such a tool.
>
> There are a couple of solutions that could be used to work around this
> issue:
>
> - The user can create their own xml description file with the
> register numbers setup to match their old tool, then load this by
> telling GDB 'set tdesc filename FILENAME'.
>
> - Update their old tool to use the newer default numbering scheme, or
> better yet add proper target description support to their tool.
>
> - We could have RISC-V GDB change to maintain the old defaults.
>
> This patch implements the last of these ideas, changing the default
> numbering to match the old behaviour.
>
> This change is only visible to targets that don't supply their own xml
> description file and instead rely on GDB's default numbering.
>
> gdb/ChangeLog:
>
> * features/riscv/32bit-cpu.xml: Add register numbers.
> * features/riscv/32bit-fpu.c: Regenerate.
> * features/riscv/32bit-fpu.xml: Add register numbers.
> * features/riscv/64bit-cpu.xml: Add register numbers.
> * features/riscv/64bit-fpu.c: Regenerate.
> * features/riscv/64bit-fpu.xml: Add register numbers.
I've had a chance to look at the patch, and fwiw, it looks good to me.
If others agree that it is OK, I think it would be nice if we pushed
the patch before I create the gdb-8.3-branch, and then create the first
pre-release (8.2.90).
--
Joel