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[PATCH] RISC-V: Fix wrong use of s0 register name.
- From: Jim Wilson <jimw at sifive dot com>
- To: gdb-patches at sourceware dot org
- Cc: andrew dot burgess at embecosm dot com, Jim Wilson <jimw at sifive dot com>
- Date: Mon, 31 Dec 2018 17:51:42 -0800
- Subject: [PATCH] RISC-V: Fix wrong use of s0 register name.
s0 is listed as both an int register name and an FP register name. The FP reg
name is wrong. This looks like a simple editting error, and has an easy fix.
Tested with riscv64-linux build and check, with no regressions.
gdb/
* riscv-tdep.c (riscv_freg_feature): Drop s0 name from f8.
---
gdb/riscv-tdep.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index ef3bb0998d..676291e56d 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -185,7 +185,7 @@ static const struct riscv_register_feature riscv_freg_feature =
{ RISCV_FIRST_FP_REGNUM + 5, { "ft5", "f5" }, true },
{ RISCV_FIRST_FP_REGNUM + 6, { "ft6", "f6" }, true },
{ RISCV_FIRST_FP_REGNUM + 7, { "ft7", "f7" }, true },
- { RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8", "s0" }, true },
+ { RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8" }, true },
{ RISCV_FIRST_FP_REGNUM + 9, { "fs1", "f9" }, true },
{ RISCV_FIRST_FP_REGNUM + 10, { "fa0", "f10" }, true },
{ RISCV_FIRST_FP_REGNUM + 11, { "fa1", "f11" }, true },
--
2.17.1