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Re: [PATCH] RISC-V: Fix xlen to flen typo in FP reg handling.

From: Jim Wilson <jimw at sifive dot com>
To: Andrew Burgess <andrew dot burgess at embecosm dot com>
Cc: gdb-patches at sourceware dot org
Date: Sat, 3 Nov 2018 13:13:58 -0700
Subject: Re: [PATCH] RISC-V: Fix xlen to flen typo in FP reg handling.
References: <20181103032033.21653-1-jimw@sifive.com> <20181103083453.GE16539@embecosm.com>

On Sat, Nov 3, 2018 at 1:34 AM Andrew Burgess
<andrew.burgess@embecosm.com> wrote:
> However, don't worry.  I'm currently working on proper target
> description support.

Do you perhaps mean XML register set support?  I started working on a
patch for that.  This is needed for our OpenOCD and QEMU support.

Meanwhile, I can hold off on this patch.

Jim

References:
- [PATCH] RISC-V: Fix xlen to flen typo in FP reg handling.
  - From: Jim Wilson
- Re: [PATCH] RISC-V: Fix xlen to flen typo in FP reg handling.
  - From: Andrew Burgess

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