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Re: [PATCH] Add support for recording xsave x86 instruction
- From: Pierre Marsais <pierre dot marsais at lse dot epita dot fr>
- To: "Metzger, Markus T" <markus dot t dot metzger at intel dot com>
- Cc: "gdb-patches at sourceware dot org" <gdb-patches at sourceware dot org>
- Date: Wed, 3 Oct 2018 01:05:23 +0100
- Subject: Re: [PATCH] Add support for recording xsave x86 instruction
- References: <20180921003827.1525-1-pierre.marsais@lse.epita.fr> <A78C989F6D9628469189715575E55B236B35E55E@IRSMSX104.ger.corp.intel.com> <20181001002516.GA31390@trigger> <A78C989F6D9628469189715575E55B236B360190@IRSMSX104.ger.corp.intel.com>
Hi,
Thanks for the quick reply.
On Mon, Oct 01, 2018 at 06:58:32AM +0000, Metzger, Markus T wrote:
> > > Also I think that we would need to check the inferior architecture to
> > > handle 32-bit compatibility mode.
> >
> > I'm not sure to follow you. In which cases 32-bit behaves differently than 64-bit ?
>
> Fewer registers. XSAVE is not writing the upper registers area.
> > >> + if (record_full_arch_list_add_mem (tmpu64 + offset, size))
> > >> + return -1;
> > >
> > > Looks like this assumes the standard (non-compacted) XSAVE format.
> > >
> > > For the compacted format, the offset must be computed by accumulating
> > > the sizes of preceding components.
> >
> > If I'm not mistaken, the compact format is only used by XSAVEC instruction, which
> > doesn't have the same opcode. The XSAVE instruction seems unrelated to this
> > format.
>
> You're right. It doesn't write the full header ,though. And there's a special case
> with XCR0[1].
Once again, thank you for finding this. I think I've addressed all your
concerns in the v3 of the patch.
Regards,
--
Pierre "Pimzero" MARSAIS,
EPITA 2018; GISTRE | ACU | LSE