Re: [PATCH 2/4] Fall back to a default value of 0 for the MISA register.

[Andrew Burgess <andrew dot burgess at embecosm dot com>]

* Jim Wilson <jimw@sifive.com> [2018-09-21 10:25:47 -0700]:

> On Fri, Sep 21, 2018 at 2:27 AM Andrew Burgess
> <andrew.burgess@embecosm.com> wrote:
> > Jim: Given that we agree that targets should definitely provide a
> > value for misa, at a minimum just returning the constant 0.  But,
> > given that GDB already defaults to 0 in some cases anyway.  And the
> > spec is quite clear that 0 is the right default value in the absence
> > of anything better, would you be OK with a patch that does return a
> > default of 0?
> 
> The patch to decode an instruction to decide whether to use a
> compressed breakpoint or not solves my main problem.  There is also
> the issue of finding FP register size, but since we only support
> rv64gc at the moment, it isn't a serious problem.

I regularly test embeded RiscV against:

  rv32im  rv32imc  rv32imf   rv32imfc

  rv64im  rv64imc  rv64imfd  rv64imfdc

with the last one of those being closes to rv64gc.  The pass rate is
broadly the same against all of these targets, so right now I consider
these equally supported for baremetal.

I understand Linux support might be different.

Thanks,

Andrew


>                                                    Also, I think the
> linker kernel may already be passing FP info via auxvec/hwcap, so I
> think we already have an alternate solution for that which just needs
> to be implemented.  I haven't looked at that yet.  So yes, I think it
> is OK to start defaulting misa to 0.
> 
> FYI I have a qemu patch, which I may someday finish, that adds XML
> register support to the RISC-V qemu system-mode port, which allows
> qemu to provide a correct value of misa.  We know that misa accesses
> already work with embedded targets via OpenOCD.  So it is just linux
> and freebsd that need to worry about misa.
> 
> The qemu patch is here, though it looks like github is confused by
> rebasing and the patch isn't readable anymore.
>     https://github.com/riscv/riscv-qemu/pull/160
> I'll have to figure out how to fix that.
> 
> Jim